LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 140

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
9.6 GPIO usage notes
UM10360
User manual
9.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port
9.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF ;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
FIO0PIN1 = 0xA5;
Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output
pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used,
only pin/bit(s) written with 1 will be changed, while those written as 0 will remain
unaffected.
Writing to the FIOPIN register enables instantaneous output of a desired value on the
parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs
on that port: zeroes in the value will produce low level pin outputs and ones in the value
will produce high level pin outputs.
A subset of a port’s pins may be changed by using the FIOMASK register to define which
pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that
will be changed, and ones for all others. Solution 2 from
output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as
they were before.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Section 9.6.1
UM10360
above illustrates
© NXP B.V. 2010. All rights reserved.
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