LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 29

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

4.1 Summary of clocking and power control functions
UM10360
User manual
Fig 7.
Clock generation for the LPC17xx
osc_clk
rtc_clk
irc_osc
PCLK_WDT
This section describes the generation of the various clocks needed by the LPC17xx and
options of clock source selection, as well as power control and wake-up from reduced
power modes. Functions described in the following subsections include:
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UM10360
Chapter 4: LPC17xx Clocking and power control
Rev. 2 — 19 August 2010
Oscillators
Clock source selection
PLLs
Clock dividers
APB dividers
Power control
Wake-up timer
External clock output
sysclk
watchdog clock select
system clock select
All information provided in this document is subject to legal disclaimers.
CLKSRCSEL[1:0]
main PLL
(PLL0...)
settings
WDCLKSEL[1:0]
USB PLL settings
Main PLL
USB PLL
(PLL1...)
Rev. 2 — 19 August 2010
(PLL1)
(PLL0)
(PLL0CON)
CPU PLL
select
`
pllclk
CPU clock divider setting
USB clock divider setting
USBCLKCFG[3:0]
CCLKCFG[7:0]
Divider
Divider
Clock
Clock
CPU
USB
(PLL1CON)
Peripheral
USB PLL
Divider
select
Clock
usb_clk
wd_clk
pclk1
pclk2
pclk4
pclk8
cclk
© NXP B.V. 2010. All rights reserved.
User manual
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