LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 248

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 245. Set Device Status command bit description
UM10360
User manual
Bit
4
7:5
Symbol
RST
-
11.12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
11.12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
Value
0
1
The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in
Remark: To ensure correct operation, the DEV_STAT bit of USBDevIntSt must be cleared
before executing the Get Device Status command.
Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.
Description
Bus Reset bit. On a bus reset, the device will automatically go to the default
state. In the default state:
Note: Bus resets are ignored when the device is not connected (CON=0).
This bit is cleared when read.
This bit is set when the device receives a bus reset. A DEV_STAT interrupt is
generated.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
•
•
•
•
•
•
•
•
Device is unconfigured.
Will respond to address 0.
Control endpoint will be in the Stalled state.
All endpoints are unrealized except control endpoints EP0 and EP1.
Data toggling is reset for all endpoints.
All buffers are cleared.
There is no change to the endpoint interrupt status.
DEV_STAT interrupt is generated.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 2 — 19 August 2010
245.
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
NA
248 of 840