LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 433

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.6.3 Slave Receiver mode
After a repeated START condition, I
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, write any of the Slave Address registers (I2ADR0-3) and Slave
Mask registers (I2MASK0-3) and write the I
in
Table 382. I2C0CONSET and I2C1CONSET used to configure Slave mode
I2EN must be set to 1 to enable the I
any of its own slave addresses or the General Call address. The STA, STO and SI bits are
set to 0.
After I2ADR and I2CONSET are initialized, the I
its any of its own slave addresses or General Call address followed by the data direction
bit. If the direction bit is 0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it
enters slave transmitter mode. After the address and direction bit have been received, the
SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to
Table 400
Bit
Symbol
Value
Fig 87. A Master Receiver switches to Master Transmitter after sending repeated START
Table
S
From master to slave
From slave to master
SLA
382.
for the status codes and actions.
7
-
-
R
All information provided in this document is subject to legal disclaimers.
A
6
I2EN
1
Rev. 2 — 19 August 2010
DATA
n bytes data transmitted
5
STA
0
A
2
C may switch to the master transmitter mode.
2
DATA
C function. AA bit must be set to 1 to acknowledge
4
STO
0
2
C Control Set register (I2CONSET) as shown
A
2
Sr
C interface waits until it is addressed by
3
SI
0
SLA
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
SLA = Slave Address
Sr = Repeated START condition
Chapter 19: LPC17xx I2C0/1/2
2
AA
1
W
A
UM10360
1
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-
© NXP B.V. 2010. All rights reserved.
DATA
A
0
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