LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 241

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 237. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0x5000 C2B4) bit description
Table 238. USB System Error Interrupt Status register (USBSysErrIntSt - address 0x5000 C2B8) bit description
Table 239. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0x5000 C2BC) bit description
Table 240. USB System Error Interrupt Set register (USBSysErrIntSet - address 0x5000 C2C0) bit description
11.11 Interrupt handling
UM10360
User manual
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Symbol
EPxx
Symbol
EPxx
Symbol
EPxx
Symbol
EPxx
11.10.7.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0x5000 C2B8)
11.10.7.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0x5000 C2BC)
11.10.7.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0x5000 C2C0)
Value
0
1
Value
0
1
Value
0
1
Value
0
1
If a system error (AHB bus error) occurs when transferring the data or when fetching or
updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read-only
register.
Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntClr is a write-only register.
Writing one to a bit in this register sets the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntSet is a write-only register.
This section describes how an interrupt event on any of the endpoints is routed to the
Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event
handling, see
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been successfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section
Description
Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.
No effect.
Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
Description
Set endpoint xx (2 ≤ xx ≤ 31) new DD interrupt request.
No effect.
Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
Description
Set endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.
No effect.
Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
Description
Endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request.
There is no System Error Interrupt request for endpoint xx.
There is a System Error Interrupt request for endpoint xx.
11.12.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.
Figure
All information provided in this document is subject to legal disclaimers.
29.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
Reset value
0
Reset value
Reset value
0
0
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