LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 599

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 556. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C)
Table 557. DMA Configuration register (DMACConfig - 0x5000 4030)
Table 558. DMA Synchronization register (DMACSync - 0x5000 4034)
UM10360
User manual
Bit
15:0
31:16
Bit
0
1
31:2
Bit
15:0
31:16
Name
SoftLSReq
-
Name
E
M
-
Name
DMACSync
-
31.5.13 DMA Configuration register (DMACConfig - 0x5000 4030)
31.5.14 DMA Synchronization register (DMACSync - 0x5000 4034)
The DMACConfig Register is read/write and configures the operation of the DMA
Controller. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
Table 557
The DMACSync Register is read/write and enables or disables synchronization logic for
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the
synchronization logic for a particular group of DMA requests. This register is reset to 0,
enabling synchronization logic by default.
DMACSync Register.
shows the bit assignments of the DMACConfig Register.
Function
Software last single transfer request flags for each of 16 possible sources. Each bit
represents one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last single transfer request for the corresponding
request line.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
DMA Controller enable:
0 = disabled (default). Disabling the DMA Controller reduces power consumption.
1 = enabled.
AHB Master endianness configuration:
0 = little-endian mode (default).
1 = big-endian mode.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Controls the synchronization logic for DMA request signals. Each bit represents one
set of DMA request lines as described in the preceding text:
0 - synchronization logic for the corresponding DMA request signals are enabled.
1 - synchronization logic for the corresponding request line signals are disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 558
shows the bit assignments of the
UM10360
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