LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 150

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
10.11 Ethernet MAC register definitions
Table 129. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description
UM10360
User manual
15
31:16 -
Bit
0
1
2
3
4
7:5
8
9
10
11
13:12 -
14
Symbol
RECEIVE ENABLE
PASS ALL RECEIVE
FRAMES
RX FLOW CONTROL When enabled (set to ’1’), the MAC acts upon received PAUSE Flow Control
TX FLOW CONTROL When enabled (set to ’1’), PAUSE Flow Control frames are allowed to be
LOOPBACK
-
RESET TX
RESET MCS / TX
RESET RX
RESET MCS / RX
SIMULATION RESET Setting this bit will cause a reset to the random number generator within the
SOFT RESET
10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000)
10.11.2 MAC Configuration Register 2 (MAC2 - 0x5000 0004)
This section defines the bits in the individual registers of the Ethernet block register map.
The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit
definition is shown in
The MAC configuration register 2 (MAC2) has an address of 0x5000 0004. Its bit
definition is shown in
Function
Set this to allow receive frames to be received. Internally the MAC synchronizes
this control bit to the incoming receive stream.
When enabled (set to ’1’), the MAC will pass all frames regardless of type (normal
vs. Control). When disabled, the MAC does not pass valid Control frames.
frames. When disabled, received PAUSE Flow Control frames are ignored.
transmitted. When disabled, Flow Control frames are blocked.
Setting this bit will cause the MAC Transmit interface to be looped back to the MAC
Receive interface. Clearing this bit results in normal operation.
Unused
Setting this bit will put the Transmit Function logic in reset.
Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic
implements flow control.
Setting this bit will put the Ethernet receive logic in reset.
Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic
implements flow control.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Transmit Function.
Setting this bit will put all modules within the MAC in reset except the Host
Interface.
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table
Table
Rev. 2 — 19 August 2010
129.
130.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
150 of 840
Reset
value
0
0
0
0
0
0x0
0
0
0
0x0
0x0
0
1
0x0