LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 647

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
34.2 ARM Cortex-M3 User Guide: Instruction Set
Table 612. Cortex-M3 instructions
UM10360
User manual
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN, CMNS
CMP, CMPS
CPSID
CPSIE
DMB
DSB
EOR, EORS
34.2.1 Instruction set summary
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
-
Rd, Rm
Rn, Op2
Rn, Op2
iflags
iflags
-
-
{Rd,} Rn, Op2
The processor implements a version of the Thumb instruction set.
supported instructions.
Note
In
For more information on the instructions and operands, see the instruction descriptions.
•
•
•
•
•
Table
angle brackets, <>, enclose alternative forms of the operand
braces, {}, enclose optional operands
the Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
most instructions can use an optional condition code suffix.
612:
All information provided in this document is subject to legal disclaimers.
Brief description
Add with Carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic Shift Right
Branch
Bit Field Clear
Bit Field Insert
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Zero
Clear Exclusive
Count leading zeros
Compare Negative
Compare
Change Processor State, Disable Interrupts
Change Processor State, Enable Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
Flags
N,Z,C,V
N,Z,C,V
N,Z,C,V
-
N,Z,C
N,Z,C
-
-
-
N,Z,C
-
-
-
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z,C
Table 612
UM10360
© NXP B.V. 2010. All rights reserved.
Page
Section 34.2.5.1
Section 34.2.5.1
Section 34.2.5.1
Section 34.2.4.1
Section 34.2.5.2
Section 34.2.5.3
Section 34.2.9.1
Section 34.2.8.1
Section 34.2.8.1
Section 34.2.5.2
Section 34.2.10.1
Section 34.2.9.1
Section 34.2.9.1
Section 34.2.9.1
Section 34.2.9.2
Section 34.2.9.2
Section 34.2.4.9
Section 34.2.5.4
Section 34.2.5.5
Section 34.2.5.5
Section 34.2.10.2
Section 34.2.10.2
Section 34.2.10.3
Section 34.2.10.4
Section 34.2.5.2
lists the
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