LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 810

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 389. I
Table 390. I
Table 391. I
Table 392. I
Table 393. I
Table 394. Example I
Table 395. Abbreviations used to describe an I
Table 396. I2CONSET used to initialize Master Transmitter
Table 397. I2CONSET used to initialize Slave Receiver
Table 398. Master Transmitter mode. . . . . . . . . . . . . . . .457
Table 399. Master Receiver mode. . . . . . . . . . . . . . . . . .458
Table 400. Slave Receiver mode. . . . . . . . . . . . . . . . . . .459
Table 401. Slave Transmitter mode. . . . . . . . . . . . . . . . .461
Table 402. Miscellaneous States . . . . . . . . . . . . . . . . . . .462
Table 403. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .475
Table 404. I2S register map. . . . . . . . . . . . . . . . . . . . . . .476
Table 405: Digital Audio Output register (I2SDAO - address
Table 406: Digital Audio Input register (I2SDAI - address
Table 407: Transmit FIFO register (I2STXFIFO - address
Table 408: Receive FIFO register (I2RXFIFO - address
Table 409: Status Feedback register (I2SSTATE - address
Table 410: DMA Configuration register 1 (I2SDMA1 -
Table 411: DMA Configuration register 2 (I2SDMA2 -
Table 412: Interrupt Request Control register (I2SIRQ -
Table 413: Transmit Clock Rate register (I2TXRATE -
UM10360
User manual
I2C1MMCTRL- 0x4005 C01C; I
I2C2MMCTRL- 0x400A 001C) bit description 444
I2CDATA_BUFFER - 0x4001 C02C; I
I2C1DATA_BUFFER- 0x4005 C02C; I
I2C2DATA_BUFFER- 0x400A 002C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .446
I2C0ADR[0, 1, 2, 3]- 0x4001 C0[0C, 20, 24, 28];
I
0x4005 C0[0C, 20, 24, 28]; I
3] - address 0x400A 00[0C, 20, 24, 28]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .446
I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34, 38, 3C];
I
0x4005 C0[30, 34, 38, 3C]; I
2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447
I2C0SCLH - address 0x4001 C010; I
I2C1SCLH - address 0x4005 C010; I
I2C2SCLH - 0x400A 0010) bit description . . .447
I2C0SCLL: 0x4001 C014; I
0x4005 C014; I
description . . . . . . . . . . . . . . . . . . . . . . . . . . .447
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .449
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
0x400A 8000) bit description . . . . . . . . . . . . .476
0x400A 8004) bit description . . . . . . . . . . . . .477
0x400A 8008) bit description . . . . . . . . . . . . .477
0x400A 800C) bit description . . . . . . . . . . . . .478
0x400A 8010) bit description . . . . . . . . . . . . .478
address 0x400A 8014) bit description . . . . . .478
address 0x400A 8018) bit description . . . . . .479
address 0x400A 801C) bit description . . . . . .479
2
2
2
2
2
2
2
C1, I2C1ADR[0, 1, 2, 3] - address
C1, I2C1MASK[0, 1, 2, 3] - address
C Data buffer register (I2DATA_BUFFER: I
C Slave Address registers (I2ADR0 to 3: I
C Mask registers (I2MASK0 to 3: I
C SCL HIGH Duty Cycle register (I2SCLH: I
C SCL Low duty cycle register (I2SCLL: I
2
C clock rates. . . . . . . . . . . . . . . . .448
2
C2 - I2C2SCLL: 0x400A 0014) bit
2
2
2
C1 - I2C1SCLL:
C2, I2C2ADR[0, 1, 2,
C2, I2C2MASK[0, 1,
2
All information provided in this document is subject to legal disclaimers.
C2,
2
2
2
2
C
2
C0,
C1,
C2,
2
C1,
C2,
Rev. 2 — 19 August 2010
2
2
C0 -
2
2
C0,
C0,
C0,
Table 414: Receive Clock Rate register (I2SRXRATE -
Table 415: Transmit Clock Rate register (I2TXBITRATE -
Table 416: Receive Clock Rate register (I2SRXBITRATE -
Table 417: Transmit Mode Control register (I2STXMODE -
Table 418: Receive Mode Control register (I2SRXMODE -
Table 419: I2S transmit modes . . . . . . . . . . . . . . . . . . . . 484
Table 420: I2S receive modes . . . . . . . . . . . . . . . . . . . . 486
Table 421. Conditions for FIFO level comparison . . . . . . 488
Table 422. DMA and interrupt request generation . . . . . 488
Table 423. Status feedback in the I2SSTATE register . . 488
Table 424. Timer/Counter pin description . . . . . . . . . . . . 491
Table 425. TIMER/COUNTER0-3 register map . . . . . . . 492
Table 426. Interrupt Register (T[0/1/2/3]IR - addresses
Table 427. Timer Control Register (TCR, TIMERn: TnTCR -
Table 428. Count Control Register (T[0/1/2/3]CTCR -
Table 429. Match Control Register (T[0/1/2/3]MCR -
Table 430. Capture Control Register (T[0/1/2/3]CCR -
Table 431. External Match Register (T[0/1/2/3]EMR -
Table 432. External Match Control . . . . . . . . . . . . . . . . . 498
Table 433. Repetitive Interrupt Timer register map. . . . . 501
Table 434. RI Compare Value register (RICOMPVAL -
Table 435. RI Compare Value register (RICOMPVAL -
Table 436. RI Control register (RICTRL - address 0x400B
Table 437. RI Counter register (RICOUNTER - address
Table 438. System Tick Timer register map . . . . . . . . . . 505
Table 439. System Timer Control and status register
Table 440. System Timer Reload value register (STRELOAD
Table 441. System Timer Current value register (STCURR -
Table 442. System Timer Calibration value register
Table 443. Set and reset inputs for PWM Flip-Flops. . . . 512
Table 444. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 445. PWM1 register map . . . . . . . . . . . . . . . . . . . 514
address 0x400A 8020) bit description . . . . . . 480
address 0x400A 8024) bit description . . . . . . 481
address 0x400A 8028) bit description . . . . . . 481
address 0x400A 802C) bit description . . . . . . 481
0x400A 8030) bit description . . . . . . . . . . . . . 482
0x400A 8034) bit description . . . . . . . . . . . . . 482
0x4000 4000, 0x4000 8000, 0x4009 0000,
0x4009 4000) bit description . . . . . . . . . . . . . 493
addresses 0x4000 4004, 0x4000 8004,
0x4009 0004, 0x4009 4004) bit description . . 494
addresses 0x4000 4070, 0x4000 8070,
0x4009 0070, 0x4009 4070) bit description . . 494
addresses 0x4000 4014, 0x4000 8014,
0x4009 0014, 0x4009 4014) bit description . . 496
addresses 0x4000 4028, 0x4000 8020,
0x4009 0028, 0x4009 4028) bit description . . 497
addresses 0x4000 403C, 0x4000 803C,
0x4009 003C, 0x4009 403C) bit description . 498
address 0x400B 0000) bit description . . . . . . 501
address 0x400B 0004) bit description . . . . . . 501
0008) bit description. . . . . . . . . . . . . . . . . . . . 502
0x400B 000C) bit description. . . . . . . . . . . . . 502
(STCTRL - 0xE000 E010) bit description. . . . 505
- 0xE000 E014) bit description. . . . . . . . . . . . 506
0xE000 E018) bit description . . . . . . . . . . . . . 506
(STCALIB - 0xE000 E01C) bit description . . . 507
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
810 of 840