LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 820
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
9.5.4
9.5.5
9.5.6
9.5.6.1
9.5.6.2
9.5.6.3
9.5.6.4
9.5.6.5
Chapter 10: LPC17xx Ethernet
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.8.1
10.8.2
10.9
10.10
10.10.1
10.11
10.11.1
10.11.2
10.11.3
10.11.4
10.11.5
10.11.6
10.11.7
10.11.8
UM10360
User manual
Basic configuration . . . . . . . . . . . . . . . . . . . . 141
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Architecture and operation . . . . . . . . . . . . . . 143
DMA engine functions . . . . . . . . . . . . . . . . . . 144
Overview of DMA operation . . . . . . . . . . . . . 144
Ethernet Packet . . . . . . . . . . . . . . . . . . . . . . . 145
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 147
Registers and software interface . . . . . . . . . 148
Ethernet MAC register definitions . . . . . . . . 150
GPIO port Pin value register FIOxPIN (FIO0PIN to
FIO4PIN- 0x2009 C014 to 0x2009 C094) . . 127
Fast GPIO port Mask register FIOxMASK
(FIO0MASK to FIO4MASK - 0x2009 C010 to
0x2009 C090) . . . . . . . . . . . . . . . . . . . . . . . . 129
GPIO interrupt registers . . . . . . . . . . . . . . . . 131
GPIO overall Interrupt Status register (IOIntStatus
- 0x4002 8080) . . . . . . . . . . . . . . . . . . . . . . . 131
GPIO Interrupt Enable for port 0 Rising Edge
(IO0IntEnR - 0x4002 8090) . . . . . . . . . . . . . 131
GPIO Interrupt Enable for port 2 Rising Edge
(IO2IntEnR - 0x4002 80B0) . . . . . . . . . . . . . 132
GPIO Interrupt Enable for port 0 Falling Edge
(IO0IntEnF - 0x4002 8094) . . . . . . . . . . . . . . 133
GPIO Interrupt Enable for port 2 Falling Edge
(IO2IntEnF - 0x4002 80B4) . . . . . . . . . . . . . 134
Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Example PHY Devices . . . . . . . . . . . . . . . . . 147
Register map . . . . . . . . . . . . . . . . . . . . . . . . 148
MAC Configuration Register 1 (MAC1 -
0x5000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 150
MAC Configuration Register 2 (MAC2 -
0x5000 0004) . . . . . . . . . . . . . . . . . . . . . . . . 150
Back-to-Back Inter-Packet-Gap Register (IPGT -
0x5000 0008) . . . . . . . . . . . . . . . . . . . . . . . . 152
Non Back-to-Back Inter-Packet-Gap Register
(IPGR - 0x5000 000C) . . . . . . . . . . . . . . . . . 152
Collision Window / Retry Register (CLRT -
0x5000 0010) . . . . . . . . . . . . . . . . . . . . . . . . 153
Maximum Frame Register (MAXF - 0x5000
0014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
PHY Support Register (SUPP - 0x5000
0018) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Test Register (TEST - 0x5000 001C) . . . . . . 153
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
9.5.6.6
9.5.6.7
9.5.6.8
9.5.6.9
9.5.6.10
9.5.6.11
9.6
9.6.1
9.6.2
10.11.9
10.11.10 MII Mgmt Command Register (MCMD -
10.11.11 MII Mgmt Address Register (MADR -
10.11.12 MII Mgmt Write Data Register (MWTD -
10.11.13 MII Mgmt Read Data Register (MRDD -
10.11.14 MII Mgmt Indicators Register (MIND -
10.11.15 Station Address 0 Register (SA0 - 0x5000
10.11.16 Station Address 1 Register (SA1 - 0x5000
10.11.17 Station Address 2 Register (SA2 - 0x5000
10.12
10.12.1
10.12.2
10.12.3
10.12.4
10.12.5
10.12.6
GPIO usage notes . . . . . . . . . . . . . . . . . . . . . 140
Control register definitions . . . . . . . . . . . . . 158
GPIO Interrupt Status for port 0 Rising Edge
Interrupt (IO0IntStatR - 0x4002 8084) . . . . . 135
GPIO Interrupt Status for port 2 Rising Edge
Interrupt (IO2IntStatR - 0x4002 80A4) . . . . . 136
GPIO Interrupt Status for port 0 Falling Edge
Interrupt (IO0IntStatF - 0x4002 8088) . . . . . 136
GPIO Interrupt Status for port 2 Falling Edge
Interrupt (IO2IntStatF - 0x4002 80A8) . . . . . 137
GPIO Interrupt Clear register for port 0 (IO0IntClr
- 0x4002 808C) . . . . . . . . . . . . . . . . . . . . . . 138
GPIO Interrupt Clear register for port 0 (IO2IntClr
- 0x4002 80AC) . . . . . . . . . . . . . . . . . . . . . . 139
Example: An instantaneous output of 0s and 1s on
a GPIO port . . . . . . . . . . . . . . . . . . . . . . . . . 140
Writing to FIOSET/FIOCLR vs. FIOPIN . . . . 140
MII Mgmt Configuration Register (MCFG -
0x5000 0020) . . . . . . . . . . . . . . . . . . . . . . . . 154
0x5000 0024) . . . . . . . . . . . . . . . . . . . . . . . . 155
0x5000 0028) . . . . . . . . . . . . . . . . . . . . . . . . 155
0x5000 002C) . . . . . . . . . . . . . . . . . . . . . . . 155
0x5000 0030) . . . . . . . . . . . . . . . . . . . . . . . . 156
0x5000 0034) . . . . . . . . . . . . . . . . . . . . . . . . 156
0040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
0044) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
0048) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Command Register (Command - 0x5000
0100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Status Register (Status - 0x5000 0104) . . . . 158
Receive Descriptor Base Address Register
(RxDescriptor - 0x5000 0108) . . . . . . . . . . . 159
Receive Status Base Address Register (RxStatus
- 0x5000 010C) . . . . . . . . . . . . . . . . . . . . . . 159
Receive Number of Descriptors Register
(RxDescriptor - 0x5000 0110) . . . . . . . . . . . 159
Receive Produce Index Register
(RxProduceIndex - 0x5000 0114) . . . . . . . . 160
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
continued >>
820 of 840
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