LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 327
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 299: UART1 Modem Control Register (U1MCR - address 0x4001 0010) bit description
UM10360
User manual
Bit
0
1
3-2
4
5
6
7
31:8
Symbol
DTR Control
RTS Control
-
Loopback
Mode Select
-
RTSen
CTSen
-
15.4.9.1
15.4.9 Auto-flow control
Value Description
NA
0
1
NA
0
1
0
1
If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1
output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will
only start transmitting if the CTS1 input signal is asserted.
Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the U1RBR module and is linked to the programmed receiver FIFO trigger
level. If auto-RTS is enabled, the data-flow is controlled as follows:
When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the de-assertion of RTS1 until after it has begun sending the
additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO
has reached the previous trigger level. The re-assertion of RTS1 signals to the sending
UART to continue transmitting data.
Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode
is active.
Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is
active.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The modem loopback mode provides a mechanism to perform diagnostic loopback
testing. Serial data from the transmitter is connected internally to serial input of the
receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in
marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected
externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4
modem outputs are connected to the 4 modem inputs. As a result of these
connections, the upper 4 bits of the U1MSR will be driven by the lower 4 bits of the
U1MCR rather than the 4 modem inputs in normal mode. This permits modem status
interrupts to be generated in loopback mode by writing the lower 4 bits of U1MCR.
Disable modem loopback mode.
Enable modem loopback mode.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Disable auto-rts flow control.
Enable auto-rts flow control.
Disable auto-cts flow control.
Enable auto-cts flow control.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
327 of 840
Reset
value
0
0
0
0
0
0
0
NA
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