LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 775

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.10 System Handler Control and State Register
34.4.3.9.1 System Handler Priority Register 1
34.4.3.9.2 System Handler Priority Register 2
34.4.3.9.3 System Handler Priority Register 3
Table 663. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field,
and bits[2:0] read as zero and ignore writes.
The bit assignments are shown in
Table 664. SHPR1 register bit assignments
The bit assignments are shown in
Table 665. SHPR2 register bit assignments
The bit assignments are shown in
Table 666. SHPR3 register bit assignments
The SHCSR enables the system handlers, and indicates:
See the register summary in
shown in
Handler
Memory management fault
Bus fault
Usage fault
SVCall
PendSV
SysTick
Bits
[31:24]
[23:16]
[15:8]
[7:0]
Bits
[31:24]
[23:0]
Bits
[31:24]
[23:16]
[15:0]
•
•
the pending status of the bus fault, memory management fault, and SVC exceptions
the active status of the system handlers.
Table
667.
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Name
PRI_7
PRI_6
PRI_5
PRI_4
Name
PRI_11
-
Name
PRI_15
PRI_14
-
Rev. 2 — 19 August 2010
PRI_4
Field
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
Table 654
Table
Table
Table
Function
Reserved
Priority of system handler 6, usage fault
Priority of system handler 5, bus fault
Priority of system handler 4, memory management fault
Function
Priority of system handler 11, SVCall
Reserved
Function
Priority of system handler 15, SysTick exception
Priority of system handler 14, PendSV
Reserved
for the SHCSR attributes. The bit assignments are
Register description
Table 664
Table 665
Table 666
664.
665.
666.
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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