LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 170

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
10.14.4 Interrupt Set Register (IntSet - 0x5000 0FEC)
Table 172. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description
The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
The Interrupt Set register (IntSet) is a write-only register with an address of 0x5000 0FEC.
The interrupt set register bit definition is shown in
Table 173. Interrupt Set register (IntSet - address 0x5000 0FEC) bit description
The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14 -
Symbol
RxOverrunIntClr
RxErrorIntClr
RxFinishedIntClr
RxDoneIntClr
TxUnderrunIntClr
TxErrorIntClr
TxFinishedIntClr
TxDoneIntClr
-
SoftIntClr
WakeupIntClr
-
Symbol
RxOverrunIntSet
RxErrorIntSet
RxFinishedIntSet
RxDoneIntSet
TxUnderrunIntSet
TxErrorIntSet
TxFinishedIntSet
TxDoneIntSet
-
SoftIntSet
WakeupIntSet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Writing a ’1’ to one of these bits (0 to 7) sets the
Function
Writing a ’1’ to one of these bits clears (0 to 7) the
corresponding status bit in interrupt status register
IntStatus.
Unused
Writing a ’1’ to one of these bits (12 and/or 13) clears the
corresponding status bit in interrupt status register
IntStatus.
Unused
Function
corresponding status bit in interrupt status register
IntStatus.
Unused
Writing a ’1’ to one of these bits (12 and/or 13) sets the
corresponding status bit in interrupt status register
IntStatus.
Unused
Table
173.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
170 of 840
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0
0
0
0
0
0
0
0
0x0
0
0
0x0