LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 534
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 474. MCPWM Match 0-2 registers (MCMAT0-2 - addresses 0x400B 8030, 0x400B 8034, 0x400B 8038) bit
UM10360
User manual
Bit
31:0
Symbol
MCMAT0/1/2
description
25.7.7.1 Match register in Edge-Aligned mode
25.7.7.2 Match register in Center-Aligned mode
25.7.7.3 0 and 100% duty cycle
25.7.7 MCPWM Match 0-2 registers (MCMAT0-2 - 0x400B 8030, 0x400B 8034,
0x400B 8038)
These registers also have “write” and “operating” versions as described above for the
Limit registers, and the operating registers are also compared to the channels’ TCs. See
25.7.6
The Match and Limit registers control the MCO0-2 outputs. If a Match register is to have
any effect on its channel’s operation, it must contain a smaller value than the
corresponding Limit register.
If the channel’s CENTER bit in MCCON is 0 selecting edge-aligned mode, a match
between TC and MAT switches the channel’s B output from “active” to “passive” state. If
the channel’s CENTER and DTE bits in MCCON are both 0, the match simultaneously
switches the channel’s A output from “passive” to “active” state.
If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’s
deadtime counter to begin counting -- when the deadtime counter expires, the channel’s A
output switches from “passive” to “active” state.
If the channel’s CENTER bit in MCCON is 1 selecting center-aligned mode, a match
between TC and MAT while the TC is incrementing switches the channel’s B output from
“active” to “passive” state, and a match while the TC is decrementing switches the A
output from “active” to “passive”. If the channel’s CENTER bit in MCCON is 1 but the DTE
bit is 0, a match simultaneously switches the channel’s other output in the opposite
direction.
If the channel’s CENTER and DTE bits are both 1, a match between TC and MAT triggers
the channel’s deadtime counter to begin counting -- when the deadtime counter expires,
the channel’s B output switches from “passive” to “active” if the TC was counting up at the
time of the match, and the channel’s A output switches from “passive” to “active” if the TC
was counting down at the time of the match.
To lock a channel’s MCO outputs at the state “B active, A passive”, write its Match register
with a higher value than you write to its Limit register. The match never occurs.
To lock a channel’s MCO outputs at the opposite state, “A active, B passive”, simply write
0 to its Match register.
Match values for TC0, 1, 2.
Description
above for details of reading and writing both Limit and Match registers.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0xFFFF FFFF
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