LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 595

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 545. DMA Interrupt Status register (DMACIntStat - 0x5000 4000)
Table 546. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004)
Table 547. DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008)
UM10360
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Bit
7:0
31:8
Name
IntStat
-
Name
IntTCStat
-
Name
IntTCClear
-
31.5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000)
31.5.2 DMA Interrupt Terminal Count Request Status register
31.5.3 DMA Interrupt Terminal Count Request Clear register
31.5.4 DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
The DMACIntStat Register is read-only and shows the status of the interrupts after
masking. A 1 bit indicates that a specific DMA channel interrupt request is active. The
request can be generated from either the error or terminal count interrupt requests.
Table 545
(DMACIntTCStat - 0x5000 4004)
The DMACIntTCStat Register is read-only and indicates the status of the terminal count
after masking.
(DMACIntTCClear - 0x5000 4008)
The DMACIntTCClear Register is write-only and clears one or more terminal count
interrupt requests. When writing to this register, each data bit that contains a 1 causes the
corresponding bit in the status register (DMACIntTCStat) to be cleared. Data bits that are
0 have no effect.
The DMACIntErrStat Register is read-only and indicates the status of the error request
after masking.
shows the bit assignments of the DMACIntStat Register.
Function
Status of DMA channel interrupts after masking. Each bit represents one channel:
0 - the corresponding channel has no active interrupt request.
1 - the corresponding channel does have an active interrupt request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Terminal count interrupt request status for DMA channels. Each bit represents one
channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels.
Each bit represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 546
Table 548
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Table 547
Rev. 2 — 19 August 2010
shows the bit assignments of the DMACIntTCStat Register.
shows the bit assignments of the DMACIntErrStat Register.
shows the bit assignments of the DMACIntTCClear Register.
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
UM10360
© NXP B.V. 2010. All rights reserved.
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