LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 653
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
34.2.3.4.1 ASR
34.2.3.4.2 LSR
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or
shift operations update the carry flag except when the specified shift length is 0. The
following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is
the shift length.
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right
by n places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of
the register into the left-hand n bits of the result. See
You can use the ASR #n operation to divide the value in the register Rm by 2
result being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the
result to 0. See
You can use the LSR #n operation to divide the value in the register Rm by 2
is regarded as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
Fig 141. ASR #3
•
•
•
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
If n is 32 or more, then all the bits in the result are cleared to 0.
31
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 2 — 19 August 2010
142.
Section
34.2.3.3. If the shift length is 0, no shift occurs. Register
...
Chapter 34: Appendix: Cortex-M3 user guide
Figure
141.
5
4
3
UM10360
2
© NXP B.V. 2010. All rights reserved.
1 0
n
, if the value
n
, with the
Carry
Flag
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