LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 796
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 796 of 840
- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
34.4.5.9.1 MPU configuration for a microcontroller
34.4.5.9 MPU design hints and tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a
region that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable
unused regions to prevent any previous region settings from affecting the new MPU
setup.
Usually, a microcontroller system has only a single processor and no caches. In such a
system, program the MPU as follows:
Table 690. Memory region attributes for a microcontroller
In most microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can
make the application code more portable. The values given are for typical situations. In
special systems, such as multiprocessor designs or designs with a separate DMA engine,
the shareability attribute might be important. In these cases refer to the recommendations
of the memory device manufacturer.
Memory region TEX
Flash memory
Internal SRAM
External SRAM
Peripherals
•
•
except for the RASR, it must use aligned word accesses
for the RASR it can use byte or aligned halfword or word accesses.
All information provided in this document is subject to legal disclaimers.
b000
b000
b000
b000
Base address of both regions
Rev. 2 — 19 August 2010
C
1
1
1
0
B
0
0
1
1
S
0
1
1
1
Memory type and attributes
Normal memory, Non-shareable, write-through
Normal memory, Shareable, write-through
Normal memory, Shareable, write-back,
write-allocate
Device memory, Shareable
Chapter 34: Appendix: Cortex-M3 user guide
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
UM10360
© NXP B.V. 2010. All rights reserved.
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Offset from
base address
64KB
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