LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 388
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)
16.16.2.4 Clearing the interrupt pending bits (IntPnd 63 to 0)
16.16.2.5 Setting the message lost bit of a FullCAN message object (MsgLost 63 to 0)
16.16.2.6 Clearing the message lost bit of a FullCAN message object (MsgLost 63 to
16.16.3.1 Scenario 1: Normal case, no message lost
16.16.3 Set and clear mechanism of the FullCAN interrupt
The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN
message and if the interrupt of the according FullCAN Object is enabled (enable bit
FCANIntxEn) is set).
During the last write access from the data storage of a FullCAN message object the
interrupt pending bit of a FullCAN object (IntPndx) gets asserted.
Each of the FullCAN Interrupt Pending requests gets cleared when the semaphore bits of
a message object are cleared by Software (ARM CPU).
The Message Lost bit of a FullCAN message object gets asserted in case of an accepted
FullCAN message and when the FullCAN Interrupt of the same object is asserted already.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets asserted if the interrupt pending bit
is set already.
0)
The Message Lost bit of a FullCAN message object gets cleared when the FullCAN
Interrupt of the same object is not asserted.
During the first write access from the data storage of a FullCAN message object the
Message Lost bit of a FullCAN object (MsgLostx) gets cleared if the interrupt pending bit
is not set.
Special precaution is needed for the built-in set and clear mechanism of the FullCAN
Interrupts. The following text illustrates how the already existing Semaphore Bits (see
Section 16.16.1 “FullCAN message layout”
features (IntPndx, MsgLstx) will behave.
Figure 65
message is stored in the FullCAN Message Object Section. After storage the message is
read out by Software (ARM CPU).
below shows a typical “normal” scenario in which an accepted FullCAN
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
for more details) and how the new introduced
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
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