LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 226

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 200. USB Device Interrupt Priority register (USBDevIntPri - address 0x5000 C22C) bit description
Table 201. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit allocation
Reset value: 0x0000 0000
Table 202. USB Endpoint Interrupt Status register (USBEpIntSt - address 0x5000 C230) bit description
UM10360
User manual
Bit
0
1
31:2
Bit
0
1
2
3
4
5
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
FRAME
EP_FAST
-
Symbol
EP0RX
EP0TX
EP1RX
EP1TX
EP2RX
EP2TX
11.10.3.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0x5000 C230)
11.10.3 Endpoint interrupt registers
EP15TX
EP11TX
EP7TX
EP3TX
31
23
15
Value Description
0
1
0
1
7
Description
Endpoint 0, Data Received Interrupt bit.
Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 1, Data Received Interrupt bit.
Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.
Endpoint 2, Data Received Interrupt bit.
Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.
The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are
used in Slave mode operation.
Each physical non-isochronous endpoint is represented by a bit in this register to indicate
that it has generated an interrupt. All non-isochronous OUT endpoints generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see
Section 11.12.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page
to one in this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be
set depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a
read-only register.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
FRAME interrupt is routed to USB_INT_REQ_LP.
FRAME interrupt is routed to USB_INT_REQ_HP.
EP_FAST interrupt is routed to USB_INT_REQ_LP.
EP_FAST interrupt is routed to USB_INT_REQ_HP.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
EP15RX
EP11RX
EP7RX
EP3RX
30
22
14
6
All information provided in this document is subject to legal disclaimers.
EP14TX
EP10TX
EP6TX
EP2TX
29
21
13
5
Rev. 2 — 19 August 2010
EP14RX
EP10RX
EP6RX
EP2RX
28
20
12
4
EP13TX
EP9TX
EP5TX
EP1TX
Chapter 11: LPC17xx USB device controller
27
19
11
3
EP13RX
EP9RX
EP5RX
EP1RX
26
18
10
2
EP12TX
EP8TX
EP4TX
EP0TX
25
17
UM10360
9
1
© NXP B.V. 2010. All rights reserved.
246). A bit set
Reset value
0
0
0
0
0
0
EP12RX
EP8RX
EP4RX
EP0RX
226 of 840
24
16
8
0
0
0
Reset
value
NA