LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 222

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description
Table 190. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description
Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description
UM10360
User manual
Bit
3
4
31:5
Bit
0
1
3:2
4
31:5
Bit
0
1
2
7:3
Symbol
-
AHB_CLK_EN
-
Symbol
-
DEV_CLK_ON
-
AHB_CLK_ON
-
Symbol
USB_INT_REQ_LP
USB_INT_REQ_HP
USB_INT_REQ_DMA
-
11.10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8)
11.10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0)
11.10.2 Device interrupt registers
This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with
the register access. Software does not have to repeat this exercise for every access,
provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register.
The USB Device Controller has three interrupt lines. This register allows software to
determine their status with a single read operation. All three interrupt lines are ORed
together to a single channel of the vectored interrupt controller. This register also contains
the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write
register.
Description
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
AHB clock enable
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Device clock on. The usbclk input to the device controller is active.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
AHB clock on.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Description
Low priority interrupt line status. This bit is read-only.
High priority interrupt line status. This bit is read-only.
DMA interrupt line status. This bit is read-only.
These bits are reserved in a device-only configuration. User software should
not write ones to reserved bits. The value read from a reserved bit is not
defined. See
All information provided in this document is subject to legal disclaimers.
Table 257
Rev. 2 — 19 August 2010
for OTG configuration.
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
NA
0
NA
Reset value
NA
0
NA
0
NA
Reset value
0
0
0
NA
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