LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 553

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 496: QEI Velocity register (QEIVEL - address 0x400B C030) bit description
Table 497: QEI Velocity Capture register (QEICAP - address 0x400B C034) bit description
Table 498: QEI Velocity Compare register (VELCOMP - address 0x400B C038) bit description
Table 499: QEI Digital Filter register (FILTER - address 0x400B C03C) bit description
UM10360
User manual
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26.6.3.10 QEI Velocity register (QEIVEL - 0x400B C030)
26.6.3.12 QEI Velocity Compare register (VELCOMP - 0x400B C038)
26.6.3.13 QEI Digital Filter register (FILTER - 0x400B C03C)
26.6.3.11 QEI Velocity Capture register (QEICAP - 0x400B C034)
Description
Current velocity pulse count.
Description
Current velocity pulse count.
Description
Velocity compare value.
Description
Digital filter sampling delay
This register contains the running count of velocity pulses for the current time period.
When the velocity timer (QEITIME) overflows the contents of this register is captured in
the velocity capture register (QEICAP). After capture, this register is set to zero. This
register is also reset when the velocity reset bit (RESV) is asserted.
This register contains the most recently measured velocity of the encoder. This
corresponds to the number of velocity pulses counted in the previous velocity timer
period.The current velocity count is latched into this register when the velocity timer
overflows.
This register contains a velocity compare value. This value is compared against the
captured velocity in the velocity capture register. If the capture velocity is less than the
value in this compare register, a velocity compare interrupt (VELC_Int) will be asserted, if
enabled.
This register contains the sampling count for the digital filter. A sampling count of zero
bypasses the filter.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 26: LPC17xx Quadrature Encoder Interface (QEI)
UM10360
© NXP B.V. 2010. All rights reserved.
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