LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 498

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 431. External Match Register (T[0/1/2/3]EMR - addresses 0x4000 403C, 0x4000 803C, 0x4009 003C,
Table 432. External Match Control
UM10360
User manual
Bit
0
1
2
3
5:4
7:6
9:8
11:10 EMC3
15:12 -
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol Description
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
0x4009 403C) bit description
00
01
10
11
21.6.12 DMA operation
External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go
low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a
MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go
low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a
MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).
External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go
low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a
MATn.2 pin, in a positive-logic manner (0 = low, 1 = high).
External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go
low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a
MATn.3 pin, in a positive-logic manner (0 = low, 1 = high).
External Match Control 0. Determines the functionality of External Match 0.
encoding of these bits.
External Match Control 1. Determines the functionality of External Match 1.
encoding of these bits.
External Match Control 2. Determines the functionality of External Match 2.
encoding of these bits.
External Match Control 3. Determines the functionality of External Match 3.
encoding of these bits.
Reserved, user software should not write ones to reserved bits. The value read from a reserved
bit is not defined.
Match events for Match 0 and Match 1 in each timer can cause a DMA request, see
Section
DMA requests are generated by a match of the Timer Counter (TC) register value to either
Match Register 0 (MR0) or Match Register 1 (MR1). This is not connected to the operation
of the Match outputs controlled by the EMR register. Each match sets a DMA request flag,
which is connected to the DMA controller. In order to have an effect, the GPDMA must be
configured and the relevant timer DMA request selected as a DMA source via the
DMAREQSEL register, see
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
21.6.12.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section
31.5.15.
Chapter 21: LPC17xx Timer 0/1/2/3
Table 432
Table 432
Table 432
Table 432
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
0
0
00
00
00
00
NA