LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 479

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 411: DMA Configuration register 2 (I2SDMA2 - address 0x400A 8018) bit description
Table 412: Interrupt Request Control register (I2SIRQ - address 0x400A 801C) bit description
UM10360
User manual
Bit
0
1
7:2
11:8
15:12
19:16
31:20
Bit
0
1
7:2
11:8
15:12
19:16
31:20
Symbol
rx_dma2_enable
tx_dma2_enable
Unused
rx_depth_dma2
-
tx_depth_dma2
-
Symbol
rx_Irq_enable
tx_Irq_enable
Unused
rx_depth_irq
-
tx_depth_irq
-
20.5.7 DMA Configuration Register 2 (I2SDMA2 - 0x400A 8018)
20.5.8 Interrupt Request Control register (I2SIRQ - 0x400A 801C)
20.5.9 Transmit Clock Rate register (I2STXRATE - 0x400A 8020)
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in
The I2SIRQ register controls the operation of the I
in I2SIRQ are shown in
The MCLK rate for the I
register. The required I2STXRATE setting depends on the desired audio sample rate
desired, the format (stereo/mono) used, and the data size.
The transmitter MCLK rate is generated using a fractional rate generator, dividing down
the frequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must be
chosen to produce a frequency twice that desired for the transmitter MCLK, which must be
an integer multiple of the transmitter bit clock rate. Fractional rate generators have some
aspects that the user should be aware of when choosing settings. These are discussed in
Section
I2STXMCLK = PCLK_I2S * (X/Y) /2
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request on DMA2.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Set the FIFO level that triggers a transmit DMA request on DMA2.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
When 1, enables
When 1, enables
Unused.
Set the FIFO level on which to create an irq request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Set the FIFO level on which to create an irq request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
20.5.9.1. The equation for the fractional rate generator is:
All information provided in this document is subject to legal disclaimers.
I
I
2
2
S
S
Rev. 2 — 19 August 2010
2
Table
Table
receive interrupt.
transmit interrupt.
S transmitter is determined by the values in the I2STXRATE
405.
405.
2
2
S receive.
S transmit.
2
S interrupt request. The function of bits
Chapter 20: LPC17xx I2S
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
0
0
NA
0
NA
Reset
Value
0
0
0
0
NA
0
NA