LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 269

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

12.1 How to read this chapter
12.2 Basic configuration
12.3 Introduction
UM10360
User manual
The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758,
LPC1756, and LPC1754. On these devices, the USB controller can be configured for
device, Host, or OTG operation.
The USB controller is configured using the following registers:
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller, and I
I
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation
AHB
ATX
DMA
FS
2
1. Power: In the PCONP register
2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the
3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
6. Initialization: see
C interface controls the external OTG ATX.
UM10360
Chapter 12: LPC17xx USB Host controller
Rev. 2 — 19 August 2010
Remark: On reset, the USB block is disabled (PCUSB = 0).
USB clock or with the Main PLL (PLL0). See
PINMODE5
Power-down mode, see
Enable register.
All information provided in this document is subject to legal disclaimers.
(Section
Section
Rev. 2 — 19 August 2010
8.5).
Section
13.11.
(Table
4.8.8.
46), set bit PCUSB.
Section
Description
Advanced High-Performance Bus
Analog Transceiver
Direct Memory Access
Full Speed
4.6.1.
2
© NXP B.V. 2010. All rights reserved.
C interface. The
User manual
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