LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 708

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.9.2.1 Syntax
34.2.9.2.2 Operation
34.2.9.2.3 Restrictions
34.2.9.2.4 Condition flags
34.2.9.2.5 Examples
34.2.9.2 CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
CBZ Rn, label
CBNZ Rn, label
where:
Rn is the register holding the operand.
label is the branch destination.
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce
the number of instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
The restrictions are:
These instructions do not change the flags.
•
•
•
Rn must be in the range of R0 to R7
the branch destination must be within 4 to 130 bytes after the instruction
these instructions must not be used inside an IT block.
CMP
CMP
BEQ
BNE
CBZ
CBNZ
Rn, #0
Rn, #0
All information provided in this document is subject to legal disclaimers.
R5, target ; Forward branch if R5 is zero
R0, target ; Forward branch if R0 is not zero
label
label
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
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