LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 147
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
10.9 Pin description
UM10360
User manual
10.8.2 Example PHY Devices
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has a standard Reduced Media Independent Interface (RMII) to
connect to an external Ethernet PHY chip. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
Some examples of compatible PHY devices are shown in
Table 125. Example PHY Devices
Table 126
Interface (RMII) to the external PHY.
Table 126. Ethernet RMII pin descriptions
Table 127
the external PHY.
Table 127. Ethernet MIIM pin descriptions
Manufacturer
Broadcom
ICS
Intel
LSI Logic
Micrel
National
SMSC
Pin Name
ENET_TX_EN
ENET_TXD[1:0]
ENET_RXD[1:0]
ENET_RX_ER
ENET_CRS
ENET_REF_CLK/
ENET_RX_CLK
Pin Name
ENET_MDC
ENET_MDIO
shows the signals used for Media Independent Interface Management (MIIM) of
shows the signals used for connecting the Reduced Media Independent
All information provided in this document is subject to legal disclaimers.
Type
Output
Input/Output
Type
Output
Output
Input
Input
Input
Input
Rev. 2 — 19 August 2010
Transmit data enable
Receive data, 2 bits.
Pin Description
Transmit data, 2 bits
Receive error.
Carrier sense/data valid.
Reference clock
Pin Description
MIIM clock.
MI data input and output
Part Number(s)
BCM5221
ICS1893
LXT971A
L80223, L80225, L80227
KS8721
DP83847, DP83846, DP83843
LAN83C185
Chapter 10: LPC17xx Ethernet
Table
125.
UM10360
© NXP B.V. 2010. All rights reserved.
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