LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 428

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

19.1 Basic configuration
19.2 Features
UM10360
User manual
The I
1. Power: In the PCONP register
2. Clock: In PCLKSEL0 select PCLK_I2C0; in PCLKSEL1 select PCLK_I2C1 or
3. Pins: Select I
4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
5. Initialization: see
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UM10360
Chapter 19: LPC17xx I2C0/1/2
Rev. 2 — 19 August 2010
Remark: On reset, all I
PCLK_I2C2 (see
modes for the port pins with I
(no pull-up, no pull-down resistors) and the PINMODE_OD registers (open drain)
(See
Remark: I
compliant (see
register to support Fast Mode Plus (See
Remark: I
Remark: I
be configured to an open-drain mode via the relevant IOCON registers, and can be
used with fast mode (400 kHz) and standard mode (100 kHz) I
include an analog filter to suppress line glitches, but a similar function is performed by
the digital filter in the I
no pull-down, open drain mode.
Standard I
Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
Programmable clock allows adjustment of I
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
Supports Fast Mode Plus (I
Optional recognition of up to 4 distinct slave addresses.
Monitor mode allows observing all I
affecting the actual I
The I
2
C0/1/2 interfaces are configured using the following registers:
2
Section
C-bus can be used for test and diagnostic purposes.
2
2
2
2
C0 is not available in the 80-pin package.
C pins that do not use specialized I
C compliant bus interfaces may be configured as Master, Slave, or
All information provided in this document is subject to legal disclaimers.
C0 pins SDA0 and SCL0 are open-drain outputs and fully I
2
8.5).
C0, I
Table
Section 19.9.8.1
Section
Rev. 2 — 19 August 2010
2
C1, or I
2
C-bus traffic.
73). I
2
C block itself. These pins should be configured as: no pull-up,
2
C interfaces are enabled (PCI2C0/1/2 = 1).
4.7.3).
2
2
2
C0 can be further configured through the I2CPADCFG
C2 pins through the PINSEL registers. Select the pin
C0 only).
2
C1 or I
(Table
and
2
C-bus traffic, regardless of slave address, without
2
46), set bit PCI2C0/1/2.
C2 functions through the PINMODE registers
Section
Table
2
C transfer rates.
2
99).
19.10.1.
C pads (as identified in
2
C. These pins do not
© NXP B.V. 2010. All rights reserved.
User manual
2
Table
C-bus
428 of 840
73) can