LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 787

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 680. MPU registers summary
UM10360
User manual
Address
0xE000ED90
0xE000ED94
0xE000ED98
0xE000ED9C
0xE000EDA0
0xE000EDA4
0xE000EDA8
0xE000EDAC
0xE000EDB0
0xE000EDB4
0xE000EDB8
34.4.5.1 MPU Type Register
Name
TYPE
CTRL
RNR
RBAR
RASR
RBAR_A1
RASR_A1
RBAR_A2
RASR_A2
RBAR_A3
RASR_A3
Table 679. Memory attributes summary
Use the MPU registers to define the MPU regions and their attributes. The MPU registers
are:
The TYPE register indicates whether the MPU is present, and if so, how many regions it
supports. See the register summary in
shown in
Table 681. TYPE register bit assignments
Memory type
Normal
Bits
[31:24]
[23:16]
Type
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Table
Required
privilege
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
681.
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Shareability
Non-shared
Shared
Non-shared
Name
-
IREGION
Rev. 2 — 19 August 2010
Reset
value
0x00000800
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Other attributes
-
Non-cacheable
Write-through
Cacheable
Write-back
Cacheable
Non-cacheable
Write-through
Cacheable
Write-back
Cacheable
Function
Reserved.
Indicates the number of supported MPU instruction
regions.
Always contains 0x00 . The MPU memory map is unified
and is described by the DREGION field.
Table 680
Chapter 34: Appendix: Cortex-M3 user guide
for its attributes. The bit assignments are
Description
Table 681
Table 682
Table 683
Table 684
Table 685
Alias of RBAR, see
Alias of RASR, see
Alias of RBAR, see
Alias of RASR, see
Alias of RBAR, see
Alias of RASR, see
Description
Memory-mapped peripherals that only
a single processor uses.
Normal memory that is shared
between several processors.
Normal memory that only a single
processor uses.
Table 684
Table 685
Table 684
Table 685
Table 684
Table 685
UM10360
© NXP B.V. 2010. All rights reserved.
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