LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 445

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.8.5.1 Interrupt in Monitor mode
19.8.5.2 Loss of arbitration in Monitor mode
Table 388. I
[1]
Remark: The ENA_SCL and MATCH_ALL bits have no effect if the MM_ENA is ‘0’ (i.e. if
the module is NOT in monitor mode).
All interrupts will occur as normal when the module is in monitor mode. This means that
the first interrupt will occur when an address-match is detected (any address received if
the MATCH_ALL bit is set, otherwise an address matching one of the four address
registers).
Subsequent to an address-match detection, interrupts will be generated after each data
byte is received for a slave-write transfer, or after each byte that the module believes it
has transmitted for a slave-read transfer. In this second case, the data register will actually
contain data transmitted by some other slave on the bus which was actually addressed by
the master.
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
In monitor mode, the I
the bus master or issue an ACK. Some other slave on the bus will respond instead.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected.
Bit
2
31:3
When the ENA_SCL bit is cleared and the I
response time becomes important. To give the part more time to respond to an I
conditions, an I2DATA_BUFFER register is used
transmission time.
Symbol
MATCH_ALL
-
I
description
2
2
C Monitor mode control register (I2MMCTRL: I
C1, I2C1MMCTRL- 0x4005 C01C; I
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
2
C module will not be able to respond to a request for information by
Rev. 2 — 19 August 2010
Select interrupt register match.
When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers, I2ADR0 through I2ADR3. That is, the module will
respond as a normal slave as far as address-recognition is
concerned.
When this bit is set to ‘1’ and the
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
bits. The value read from a reserved bit is not defined.
Reserved. User software should not write ones to reserved
2
C no longer has the ability to stretch the clock, interrupt
(Section
2
C2, I2C2MMCTRL- 0x400A 001C) bit
19.8.6) to hold received data for a full 9-bit word
2
C0, I2C0MMCTRL - 0x4001 C01C;
I
Chapter 19: LPC17xx I2C0/1/2
2
C
is in monitor mode, an
2
C interrupt under these
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0
NA