LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 768

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.2.1 About IT folding
34.4.3.3 CPUID Base Register
34.4.3.4 Interrupt Control and State Register
Table 655. ACTLR bit assignments
In some situations, the processor can start executing the first instruction in an IT block
while it is still executing the IT instruction. This behavior is called IT folding, and improves
performance, However, IT folding can cause jitter in looping. If a task must avoid jitter, set
the DISFOLD bit to 1 before executing the task, to disable IT folding.
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in
are shown in
Table 656. CPUID register bit assignments
The ICSR:
Bits
[31:3]
[2]
[1]
[0]
Bits
[31:24]
[23:20]
[19:16]
[15:4]
[3:0]
•
•
provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
indicates:
– the exception number of the exception being processed
Name
-
DISFOLD
DISDEFWBUF
DISMCYCINT
Name
Implementer
Variant
Constant
PartNo
Revision
Table
All information provided in this document is subject to legal disclaimers.
656.
Rev. 2 — 19 August 2010
Function
Reserved
When set to 1, disables IT folding. see
information.
When set to 1, disables write buffer use during default memory map
accesses. This causes all bus faults to be precise bus faults but
decreases performance because any store to memory must complete
before the processor can execute the next instruction.
Remark: This bit only affects write buffers implemented in the
Cortex-M3 processor.
When set to 1, disables interruption of load multiple and store multiple
instructions. This increases the interrupt latency of the processor
because any LDM or STM must complete before the processor can
stack the current state and enter the interrupt handler.
Function
Implementer code:
0x41 = ARM
Variant number, the r value in the r n p n product revision identifier:
0x2 = r2p0
Reads as 0xF
Part number of the processor:
0xC23 = Cortex-M3
Revision number, the p value in the r n p n product revision identifier:
0x0 = r2p0
Table 654
Chapter 34: Appendix: Cortex-M3 user guide
for its attributes. The bit assignments
Section 34.4.3.2.1
UM10360
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