LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 19

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 4.
Reset block diagram including the wake-up timer
USB need_clk wake-up
Ethernet MAC wake-up
power-down
external
GPIO0 port wake-up
GPIO2 port wake-up
reset
watchdog
EINT0 wake-up
EINT1 wake-up
EINT2 wake-up
EINT3 wake-up
CAN wake-up
BOD wake-up
RTC wake-up
reset
POR
BOD
On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,
External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time
(maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the
reset signal is latched and synchronized on the IRC clock. Then the following two
sequences start simultaneously:
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 5
processor status when the LPC17xx starts up after reset. See
oscillator”
1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is
2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is
de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times
out. The boot code performs the boot tasks and may jump to the flash. If the flash is
not ready to access, the Flash Accelerator will insert wait cycles until the flash is
ready.
de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it
times out, the flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the Flash Accelerator will be granted access to the flash.
shows an example of the relationship between the RESET, the IRC, and the
for start-up of the main oscillator if selected by the user code.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
C
S
Q
internal RC
oscillator
from APB
write “1”
START
WAKE-UP TIMER
reset
Chapter 3: LPC17xx System control
COUNT 2
Reset to the
on-chip circuitry
Reset to
PCON.PD
n
Section 4.3.2 “Main
APB read of
PDBIT
in PCON
F
to other
blocks
OSC
UM10360
C
S
© NXP B.V. 2010. All rights reserved.
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