LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 588

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
31.4.1.6.1 Bus and transfer widths
31.4.1.6.2 Endian behavior
31.4.1.2 Control logic and register bank
31.4.1.3 DMA request and response interface
31.4.1.4 Channel logic and channel register bank
31.4.1.5 Interrupt request
31.4.1.6 AHB master interface
The register block stores data written or to be read across the AHB interface.
See
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
The interrupt request generates the interrupt to the ARM processor.
The DMA Controller contains one AHB master interface. The AHB master is capable of
dealing with all types of AHB transactions, including:
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
The DMA Controller can cope with both little-endian and big-endian addressing.
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided.
different source and destination combinations.
•
•
•
Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.
Locked transfers for source and destination of each stream.
Setting of protection bits for transfers on each stream.
Section 31.4.2
All information provided in this document is subject to legal disclaimers.
for information on the DMA request and response interface.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 542
shows endian behavior for
UM10360
© NXP B.V. 2010. All rights reserved.
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