LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 155

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 140. MII Mgmt Command register (MCMD - address 0x5000 0024) bit description
UM10360
User manual
Bit
0
1
31:2
-
Symbol Function
READ
SCAN
10.11.10 MII Mgmt Command Register (MCMD - 0x5000 0024)
10.11.12 MII Mgmt Write Data Register (MWTD - 0x5000 002C)
10.11.11 MII Mgmt Address Register (MADR - 0x5000 0028)
This bit causes the MII Management hardware to perform a single Read cycle. The Read data is
returned in Register MRDD (MII Mgmt Read Data).
This bit causes the MII Management hardware to perform Read cycles continuously. This is
useful for monitoring Link Fail for example.
Unused
Table 139. Clock select encoding
[1]
The MII Mgmt Command register (MCMD) has an address of 0x5000 0024. The bit
definition of this register is shown in
The MII Mgmt Address register (MADR) has an address of 0x5000 0028. The bit definition
of this register is shown in
Table 141. MII Mgmt Address register (MADR - address 0x5000 0028) bit description
The MII Mgmt Write Data register (MWTD) is a write-only register with an address of
0x5000 002C. The bit definition of this register is shown in
Clock Select
Host Clock divided by 48
Host Clock divided by 52
Host Clock divided by 56
Host Clock divided by 60
Host Clock divided by 64
Bit
4:0
7:5
12:8
31:13
The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device.
Symbol
REGISTER
ADDRESS
-
PHY ADDRESS
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
This field represents the 5-bit Register Address field of Mgmt
cycles. Up to 32 registers can be accessed.
Unused
This field represents the 5-bit PHY Address field of Mgmt
cycles. Up to 31 PHYs can be addressed (0 is reserved).
Unused
Table
Bit 5
1
1
1
1
1
141.
Bit 4
0
1
1
1
1
Table
140.
Bit 3
1
0
0
1
1
Bit 2
1
0
1
0
1
Chapter 10: LPC17xx Ethernet
Table
Maximum AHB
clock supported
120
130
140
150
160
[1]
[1]
[1]
[1]
[1]
142.
UM10360
© NXP B.V. 2010. All rights reserved.
155 of 840
Reset
value
0x0
0x0
0x0
0x0
Reset
value
0
0
0x0