LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 72

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

6.1 Features
6.2 Description
6.3 Interrupt sources
UM10360
User manual
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 User Guide
Table 50
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source, as noted.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to
operate from an external signal, the NMI function must be connected to the related device
pin (P2.10 / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be
processed. For details, refer to the Cortex-M3 User Guide that is an appendix to this User
Manual.
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UM10360
Chapter 6: LPC17xx Nested Vectored Interrupt Controller
(NVIC)
Rev. 2 — 19 August 2010
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 35 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt
Software interrupt generation
lists the interrupt sources for each peripheral function. Each peripheral device
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 34.4.2
for details of NVIC operation.
© NXP B.V. 2010. All rights reserved.
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