LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 138

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)
Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8)
[1]
Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding
port 0 pin.
Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description
Bit
7
8
9
10
11
12
13
31:14 -
Bit
0
1
2
3
4
5
6
7
8
9
10
11
14:12 -
15
16
17
18
19
20
21
22
Not available on 80-pin package.
Symbol
P2.7FEI
P2.8FEI
P2.9FEI
P2.10FEI
P2.11FEI
P2.12FEI
P2.13FEI
Symbol
P0.0CI
P0.1CI
P0.2CI
P0.3CI
P0.4CI
P0.5CI
P0.6CI
P0.7CI
P0.8CI
P0.9CI
P0.10CI
P0.11CI
P0.15CI
P0.16CI
P0.17CI
P0.18CI
P0.19CI
P0.20CI
P0.21CI
P0.22CI
bit description
[1]
[1]
[1]
[1]
[1]
All information provided in this document is subject to legal disclaimers.
[1]
[1]
[1]
Value Description
0
1
Value Description
Rev. 2 — 19 August 2010
Clear GPIO port Interrupts for P0.0
Corresponding bits in IOxIntStatR and IOxIntStatF are
unchanged.
Corresponding bits in IOxIntStatR and IOxStatF are cleared.
Clear GPIO port Interrupts for P0.1.
Clear GPIO port Interrupts for P0.2.
Clear GPIO port Interrupts for P0.3.
Clear GPIO port Interrupts for P0.4.
Clear GPIO port Interrupts for P0.5.
Clear GPIO port Interrupts for P0.6.
Clear GPIO port Interrupts for P0.7.
Clear GPIO port Interrupts for P0.8.
Clear GPIO port Interrupts for P0.9.
Clear GPIO port Interrupts for P0.10.
Clear GPIO port Interrupts for P0.11.
Reserved.
Clear GPIO port Interrupts for P0.15.
Clear GPIO port Interrupts for P0.16.
Clear GPIO port Interrupts for P0.17.
Clear GPIO port Interrupts for P0.18.
Clear GPIO port Interrupts for P0.19.
Clear GPIO port Interrupts for P0.20.
Clear GPIO port Interrupts for P0.21.
Clear GPIO port Interrupts for P0.22.
Status of Falling Edge Interrupt for P2.7.
Status of Falling Edge Interrupt for P2.8.
Status of Falling Edge Interrupt for P2.9.
Status of Falling Edge Interrupt for P2.10.
Status of Falling Edge Interrupt for P2.11.
Status of Falling Edge Interrupt for P2.12.
Status of Falling Edge Interrupt for P2.13.
Reserved.
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
UM10360
© NXP B.V. 2010. All rights reserved.
138 of 840
Reset
value
0
0
0
0
0
0
0
NA
Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
NA
0
0
0
0
0
0
0
0