LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 572

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
28.4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004)
28.4.3 Watchdog Feed register (WDFEED - 0x4000 0008)
28.4.4 Watchdog Timer Value register (WDTV - 0x4000 000C)
28.4.5 Watchdog Timer Clock Source Selection register (WDCLKSEL -
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
Table 525: Watchdog Constant register (WDTC - address 0x4000 0004) bit description
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
Table 526: Watchdog Feed register (WDFEED - address 0x4000 0008) bit description
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
Table 527: Watchdog Timer Value register (WDTV - address 0x4000 000C) bit description
0x4000 0010)
This register allows selecting the clock source for the Watchdog timer. The possibilities are the
Internal RC oscillator (IRC) or the APB peripheral clock (pclk). The function of bits in WDCLKSEL
are shown in
modified. On reset, the clock source selection bits are always unlocked.
When the IRC is chosen as the watchdog clock source, the watchdog timer can remain
running in deep sleep mode, and can reset or wake up the device from that mode.
Bit
31:0
Bit
7:0
31:8
Bit
31:0
Symbol
Feed
-
Symbol
Count
Symbol
Count
Table 528
All information provided in this document is subject to legal disclaimers.
Description
Feed value should be 0xAA followed by 0x55.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
Counter timer value.
Description
Watchdog time-out interval.
. The clock source selection can be locked by software, so that it cannot be
Rev. 2 — 19 August 2010
Chapter 28: LPC17xx Watchdog Timer (WDT)
WDCLK
× 256 × 4.
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0x0000 00FF
Reset Value
0x0000 00FF
572 of 840
NA
Reset
Value
NA