LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 824
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
12.4.2
12.4.2.1
Chapter 13: LPC17xx USB OTG
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.7.1
13.7.2
13.7.3
13.8
13.8.1
13.8.2
13.8.3
13.8.4
13.8.5
13.8.6
13.8.7
13.8.8
13.8.9
Chapter 14: LPC17xx UART0/2/3
14.1
14.2
14.3
14.4
14.4.1
14.4.2
UM10360
User manual
How to read this chapter . . . . . . . . . . . . . . . . 273
Basic configuration . . . . . . . . . . . . . . . . . . . . 273
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Modes of operation . . . . . . . . . . . . . . . . . . . . 274
Pin configuration . . . . . . . . . . . . . . . . . . . . . . 275
Register description . . . . . . . . . . . . . . . . . . . 277
Basic configuration . . . . . . . . . . . . . . . . . . . . 298
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 299
Register description . . . . . . . . . . . . . . . . . . . 299
Software interface. . . . . . . . . . . . . . . . . . . . . 271
Register map . . . . . . . . . . . . . . . . . . . . . . . . 271
Connecting the USB port to an external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Connecting USB as a host . . . . . . . . . . . . . . 276
Connecting USB as device . . . . . . . . . . . . . . 276
USB Interrupt Status Register (USBIntSt -
0x5000 C1C0) . . . . . . . . . . . . . . . . . . . . . . . 277
OTG Interrupt Status Register (OTGIntSt -
0x5000 C100) . . . . . . . . . . . . . . . . . . . . . . . . 278
OTG Interrupt Enable Register (OTGIntEn -
0x5000 C104) . . . . . . . . . . . . . . . . . . . . . . . . 278
OTG Interrupt Set Register (OTGIntSet -
0x5000 C20C) . . . . . . . . . . . . . . . . . . . . . . . 278
OTG Interrupt Clear Register (OTGIntClr -
0x5000 C10C) . . . . . . . . . . . . . . . . . . . . . . . 279
OTG Status and Control Register (OTGStCtrl -
0x5000 C110) . . . . . . . . . . . . . . . . . . . . . . . . 279
OTG Timer Register (OTGTmr - 0x5000
C114) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
OTG Clock Control Register (OTGClkCtrl -
0x5000 CFF4). . . . . . . . . . . . . . . . . . . . . . . . 280
OTG Clock Status Register (OTGClkSt -
0x5000 CFF8). . . . . . . . . . . . . . . . . . . . . . . . 281
UARTn Receiver Buffer Register (U0RBR -
0x4000 C000, U2RBR - 0x4009 8000, U3RBR -
0x4009 C000 when DLAB = 0) . . . . . . . . . . . 301
UARTn Transmit Holding Register (U0THR -
0x4000 C000, U2THR - 0x4009 8000, U3THR -
0x4009 C000 when DLAB = 0) . . . . . . . . . . . 301
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
12.4.2.2
13.8.10
13.8.11
13.8.12
13.8.13
13.8.14
13.8.15
13.8.16
13.9
13.9.1
13.9.2
13.10
13.10.1
13.10.1.1 Host clock request signals . . . . . . . . . . . . . . 296
13.10.2
13.11
14.4.3
14.4.4
14.4.5
HNP support . . . . . . . . . . . . . . . . . . . . . . . . . 286
Clocking and power management. . . . . . . . 294
USB OTG controller initialization . . . . . . . . 296
USB Host Register Definitions . . . . . . . . . . . 272
I2C Receive Register (I2C_RX - 0x5000
C300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
I2C Transmit Register (I2C_TX - 0x5000
C300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
I2C Status Register (I2C_STS - 0x5000
C304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
I2C Control Register (I2C_CTL - 0x5000
C308) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
I2C Clock High Register (I2C_CLKHI -
0x5000 C30C) . . . . . . . . . . . . . . . . . . . . . . . 285
I2C Clock Low Register (I2C_CLKLO -
0x5000 C310) . . . . . . . . . . . . . . . . . . . . . . . 285
Interrupt handling . . . . . . . . . . . . . . . . . . . . . 285
B-device: peripheral to host switching . . . . . 287
Remove D+ pull-up . . . . . . . . . . . . . . . . . . . . 289
Add D+ pull-up . . . . . . . . . . . . . . . . . . . . . . . . 290
A-device: host to peripheral HNP switching. 290
Set BDIS_ACON_EN in external OTG
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Clear BDIS_ACON_EN in external OTG trans-
ceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Discharge V
Load and enable OTG timer . . . . . . . . . . . . . 294
Stop OTG timer . . . . . . . . . . . . . . . . . . . . . . . 294
Suspend host on port 1 . . . . . . . . . . . . . . . . . 294
Device clock request signals . . . . . . . . . . . . 295
Power-down mode support . . . . . . . . . . . . . 296
UARTn Divisor Latch LSB register (U0DLL -
0x4000 C000, U2DLL - 0x4009 8000, U3DLL -
0x4009 C000 when DLAB = 1) and UARTn Divisor
Latch MSB register (U0DLM - 0x4000 C004,
U2DLL - 0x4009 8004, U3DLL - 0x4009 C004
when DLAB = 1). . . . . . . . . . . . . . . . . . . . . . 301
UARTn Interrupt Enable Register (U0IER -
0x4000 C004, U2IER - 0x4009 8004, U3IER -
0x4009 C004 when DLAB = 0) . . . . . . . . . . 302
UARTn Interrupt Identification Register (U0IIR -
0x4000 C008, U2IIR - 0x4009 8008, U3IIR -
0x4009 C008) . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 35: Supplementary information
BUS
. . . . . . . . . . . . . . . . . . . . . . . 293
UM10360
© NXP B.V. 2010. All rights reserved.
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