LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 483
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
20.6 I
UM10360
User manual
2
S transmit and receive interfaces
The I
information. Some details of I
When switching between data width or modes the I
control register in order to ensure correct synchronization. It is advisable to set the stop bit
also until sufficient data has been written in the transmit FIFO. Note that when stopped
data output is muted.
All data accesses to FIFOs are 32 bits.
A data sample in the FIFO consists of:
Data is read from the transmit FIFO after the falling edge of WS, it will be transferred to
the transmit clock domain after the rising edge of WS. On the next falling edge of WS the
left data will be loaded in the shift register and transmitted and on the following rising edge
of WS the right data is loaded and transmitted.
The receive channel will start receiving data after a change of WS. When word select
becomes low it expects this data to be left data, when WS is high received data is
expected to be right data. Reception will stop when the bit counter has reached the limit
set by wordwidth. On the next change of WS the received data will be stored in the
appropriate hold register. When complete data is available it will be written into the receive
FIFO.
•
•
•
•
•
•
•
•
•
When the FIFO is empty, the transmit channel will repeat transmitting the same data
until new data is written to the FIFO.
When mute is true, the data value 0 is transmitted.
When mono is false, two successive data words are respectively left and right data.
Data word length is determined by the wordwidth value in the configuration register.
There is a separate wordwidth value for the receive channel and the transmit channel.
– 0: word is considered to contain four 8-bit data words.
– 1: word is considered to contain two 16-bit data words.
– 3: word is considered to contain one 32-bit data word.
When the transmit FIFO contains insufficient data the transmit channel will repeat
transmitting the last data until new data is available. This can occur when the
microprocessor or the DMA at some time is unable to provide new data fast enough.
Because of this delay in new data there is a need to fill the gap, which is
accomplished by continuing to transmit the last sample. The data is not muted as this
would produce an noticeable and undesirable effect in the sound.
The transmit channel and the receive channel only handle 32-bit aligned words, data
chunks must be clipped or extended to a multiple of 32 bits.
1×32 bits in 8-bit or 16-bit stereo modes.
1×32 bits in mono modes.
2×32 bits, first left data, second right data, in 32-bit stereo modes.
2
S interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
2
S implementation are:
Figure 113
2
shows the possible data sequences.
S must be reset via the reset bit in the
Chapter 20: LPC17xx I2S
UM10360
© NXP B.V. 2010. All rights reserved.
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