LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 167

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
10.13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208)
10.13.4 Hash Filter Table LSBs Register (HashFilterL - 0x5000 0210)
Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit
The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be
cleared by writing the RxFilterWoLClear register.
The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only
register with an address of 0x5000 0208.
Table 167
Table 167. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x5000 0208) bit
The bits in this register are write-only; writing resets the corresponding bits in the
RxFilterWoLStatus register.
The Hash Filter table LSBs register (HashFilterL) has an address of 0x5000 0210.
Table 168
found in
Table 168. Hash Filter Table LSBs register (HashFilterL - address 0x5000 0210) bit
Bit
6
7
8
31:9 -
Bit
0
1
2
3
4
5
6
7
8
31:9 -
Bit
31:0
Symbol
-
RxFilterWoL
MagicPacketWoL
Symbol
AcceptUnicastWoLClr
AcceptBroadcastWoLClr
AcceptMulticastWoLClr
AcceptUnicastHashWoLClr
AcceptMulticastHashWoLClr
AcceptPerfectWoLClr
-
RxFilterWoLClr
MagicPacketWoLClr
Symbol
HashFilterL
Section 10.17.10 “Receive filtering” on page
lists the definition of the individual bits in the register.
lists the bit definitions of the register. Details of Hash filter table use can be
description
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Bits 31:0 of the imperfect filter hash table for receive
filtering.
Function
Unused
When the value is ’1’, the receive filter caused WoL.
When the value is ’1’, the magic packet filter caused
WoL.
Unused
Function
When a ’1’ is written to one of these bits (0 to 5), the
corresponding status bit in the RxFilterWoLStatus
register is cleared.
Unused
When a ’1’ is written to one of these bits (7 and/or 8),
the corresponding status bit in the RxFilterWoLStatus
register is cleared.
Unused
198.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
167 of 840
Reset
value
0x0
0
0
0x0
Reset
value
0
0
0
0
0
0
0x0
0
0
0x0
Reset
value
0x0