LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 328

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 300: Modem status interrupt generation
UM10360
User manual
Enable Modem Status
Interrupt (U1ER[3])
0
1
1
1
1
1
1
1
1
Fig 48. Auto-RTS Functional Timing
UART1 Rx
UART1 Rx
UART1 Rx
FIFO read
FIFO level
RTS1 pin
15.4.9.2 Auto-CTS
start
N-1
byte N
If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of
RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to
0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the
receive FIFO contains 8 bytes
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the U1TSR module checks CTS1 input before sending the next
data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS1 must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the U1MSR will be set though.
generating a Modem Status interrupt.
CTSen
(U1MCR[7])
x
0
0
0
1
1
1
1
1
stop
start
N
CTS Interrupt
Enable (U1IER[7])
x
x
x
x
0
0
1
1
1
All information provided in this document is subject to legal disclaimers.
bits0..7
N-1
Rev. 2 — 19 August 2010
stop
N-2
(Table 297 on page
Delta CTS
(U1MSR[0])
x
0
1
x
x
x
0
1
x
N-1
N-2
Delta DCD or Trailing Edge RI
or Delta DSR (U1MSR[3] or
U1MSR[2] or U1MSR[1])
x
0
x
1
0
1
0
x
1
Table 300
325). The RTS1 output will be
M+2
lists the conditions for
Chapter 15: LPC17xx UART1
M+1
M
start
UM10360
© NXP B.V. 2010. All rights reserved.
bits0..7
Modem Status
Interrupt
No
No
Yes
Yes
No
Yes
No
Yes
Yes
M-1
328 of 840
stop