LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 716

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.10.2.1 Syntax
34.2.10.2.2 Operation
34.2.10.2.3 Restrictions
34.2.10.2.4 Condition flags
34.2.10.2.5 Examples
34.2.10.2 CPS
Change Processor State.
CPSeffect iflags
where:
effect is one of:
iflags is a sequence of one or more flags:
CPS changes the PRIMASK and FAULTMASK special register values. See
Section 34.3.1.3.6 “Exception mask registers”
The restrictions are:
This instruction does not change the condition flags.
•
•
IE Clears the special purpose register.
ID Sets the special purpose register
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
use CPS only from privileged software, it has no effect if used in unprivileged software.
CPS cannot be conditional and so must not be used inside an IT block.
CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
for more information about these registers.
UM10360
© NXP B.V. 2010. All rights reserved.
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