LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 429

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
19.3 Applications
19.4 Description
UM10360
User manual
Interfaces to external I
other microcontrollers, etc.
A typical I
direction bit (R/W), two types of data transfers are possible on the I
The LPC17xx I
transmitter mode, master receiver mode, slave transmitter mode and slave receiver
mode.
•
•
•
I
supports functions described in the I
Mode Plus). This includes multi-master operation and allows powering off this device
in a working system while leaving the I
Data transfer from a master transmitter to a slave receiver. The first byte transmitted
by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after each received byte, unless the slave device is unable
to accept more data.
Data transfer from a slave transmitter to a master receiver. The first byte (the slave
address) is transmitted by the master. The slave then returns an acknowledge bit.
Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” is returned. The master device generates all
of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the I
released.
2
C0 is a standard I
2
C-bus configuration is shown in
2
All information provided in this document is subject to legal disclaimers.
C interfaces are byte oriented and have four operating modes: master
2
Rev. 2 — 19 August 2010
2
C standard parts, such as serial RAMs, LCDs, tone generators,
C compliant bus interface with open-drain pins. This interface
2
C specification for speeds up to 1 MHz (Fast
2
Figure
C-bus functional.
84. Depending on the state of the
Chapter 19: LPC17xx I2C0/1/2
2
C-bus will not be
2
C-bus:
UM10360
© NXP B.V. 2010. All rights reserved.
429 of 840