LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 688

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.5.6.3 Restrictions
34.2.5.6.4 Condition flags
34.2.5.6.5 Example
You can use SP and PC only in the MOV instruction, with the following restrictions:
When Rd is PC in a MOV instruction:
Remark: Though it is possible to use MOV as a branch instruction, ARM strongly
recommends the use of a BX or BLX instruction to branch for software portability to the ARM
instruction set.
If S is specified, these instructions:
•
•
•
•
•
•
•
the second operand must be a register without shift
you must not specify the S suffix.
bit[0] of the value written to the PC is ignored
a branch occurs to the address created by forcing bit[0] of that value to 0.
update the N and Z flags according to the result
can update the C flag during the calculation of Operand2, see
do not affect the V flag.
MOVS R11, #0x000B
MOV
MOVS R10, R12
MOV
MOV
MVNS R2, #0xF
All information provided in this document is subject to legal disclaimers.
R1, #0xFA05
R3, #23
R8, SP
Rev. 2 — 19 August 2010
; Write value of 0x000B to R11, flags get updated
; Write value of 0xFA05 to R1, flags are not updated
; Write value in R12 to R10, flags get updated
; Write value of 23 to R3
; Write value of stack pointer to R8
; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.2.3.3
UM10360
© NXP B.V. 2010. All rights reserved.
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