LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 730

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
The PSR bit assignments are:
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
The PSR combinations and attributes are:
Table 627.
[1]
[2]
See the instruction descriptions
more information about how to access the program status registers.
Application Program Status Register:
condition flags from previous instruction executions. See the register summary in
Table 626
Register
PSR
IEPSR
IAPSR
EAPSR
APSR
EPSR
•
•
IPSR
read all of the registers using PSR with the MRS instruction
write to the APSR using APSR with the MSR instruction.
The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
31 30 29 28 27
31 30 29 28 27 26 25 24 23
N Z C V
N
Reserved
Z C V Q ICI/IT T
for its attributes. The bit assignments are:
PSR register combinations
All information provided in this document is subject to legal disclaimers.
Q
26
ICI/IT
25 24 23
Rev. 2 — 19 August 2010
T
Type
RW
RO
RW
RW
Section 34.2.10.6 “MRS”
Reserved
[1][2]
[1]
[2]
Reserved
Reserved
The APSR contains the current state of the
Chapter 34: Appendix: Cortex-M3 user guide
16 15
16 15
Reserved
ICI/IT
ICI/IT
Reserved
and
Combination
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
10 9
10 9 8
Section 34.2.10.7 “MSR”
8
UM10360
© NXP B.V. 2010. All rights reserved.
ISR_NUMBER
ISR_NUMBER
Reserved
730 of 840
for
0
0