LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 537

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
25.8 PWM operation
UM10360
User manual
25.8.1 Pulse-width modulation
Each channel of the MCPWM has two outputs, A and B, that can drive a pair of transistors
to switch a controlled point between two power rails. Most of the time the two outputs have
opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to
delay both signals’ transitions from “passive” to “active” state so that the transistors are
never both turned on simultaneously. In a more general view, the states of each output
pair can be thought of “high”, “low”, and “floating” or “up”, “down”, and “center-off”.
Each channel’s mapping from “active” and “passive” to “high” and “low” is programmable.
After Reset, the three A outputs are passive/low, and the B outputs are active/high.
The MCPWM can perform edge-aligned and center-aligned pulse-width modulation.
Note: In timer mode, the period of a channel’s modulated MCO outputs is determined by
its Limit register, and the pulse width at the start of the period is determined by its Match
register. If it suits your way of thinking, consider the Limit register to be the “Period register”
and the Match register to be the “Pulse Width register”.
Edge-aligned PWM without dead-time
In this mode the timer TC counts up from 0 to the value in the LIM register. As shown in
Figure
point it changes to “A active”. When the TC matches the Limit register, the MCO state
changes back to “A passive”, and the TC is reset and starts counting up again.
Center-aligned PWM without dead-time
In this mode the timer TC counts up from 0 to the value in the LIM register, then counts
back down to 0 and repeats. As shown in
state is “A passive” until the TC matches the Match register, at which point it changes to “A
active”. When the TC matches the Limit register it starts counting down. When the TC
matches the Match register on the way down, the MCO state changes back to “A passive”.
Fig 122. Edge-aligned PWM waveform without dead time, POLA = 0
122, the MCO state is “A passive” until the TC matches the Match register, at which
MCOB
MCOA
All information provided in this document is subject to legal disclaimers.
0
active
passive
Rev. 2 — 19 August 2010
MAT
passive
active
timer reset
LIM
active
passive
Figure
Chapter 25: LPC17xx Motor control PWM
MAT
123, while the timer counts up, the MCO
passive
active
timer reset
LIM
UM10360
© NXP B.V. 2010. All rights reserved.
POLA = 0
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