LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 444

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
19.8.5 I
Table 387. I
0x4001 C01C; I
0x400A 001C)
This register controls the Monitor mode which allows the I
the I
Table 388. I
Bit
7:0
31:8
Bit
0
1
2
C Monitor mode control register (I2MMCTRL: I
2
C-bus without actually participating in traffic or interfering with the I
Symbol Description
Data
-
Symbol
MM_ENA
ENA_SCL
0x4005 C008; I
I
description
2
2
2
C Data register (I2DAT: I
C Monitor mode control register (I2MMCTRL: I
C1, I2C1MMCTRL- 0x4005 C01C; I
All information provided in this document is subject to legal disclaimers.
This register holds data values that have been received or are to be
transmitted.
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
C1, I2C1MMCTRL- 0x4005 C01C; I
Value Description
0
1
0
1
Rev. 2 — 19 August 2010
2
C2, I2C2DAT - 0x400A 0008) bit description
Monitor mode enable.
Monitor mode disabled.
The
SDA output will be put in high impedance mode. This
prevents the
(including ACK) onto the
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the
SCL output enable.
When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the
When this bit is set, the
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the
module can “stretch” the clock line (hold it low) until it has
had time to respond to an
I
2
C
2
module will enter monitor mode. In this mode the
I
C0, I2C0DAT - 0x4001 C008; I
2
C
clock line.
I
2
C
I
2
module from outputting data of any kind
C
2
C2, I2C2MMCTRL- 0x400A 001C) bit
clock line.
I
2
I
C
2
I
C
2
module may exercise the same
C
data bus.
interrupt.
2
C0, I2C0MMCTRL - 0x4001 C01C;
Chapter 19: LPC17xx I2C0/1/2
2
C module to monitor traffic on
2
C0, I2C0MMCTRL -
[1]
2
2
C2, I2C2MMCTRL-
C1, I2C1DAT -
UM10360
© NXP B.V. 2010. All rights reserved.
2
I
C-bus.
2
C
444 of 840
Reset
value
0
NA
Reset
value
0
0