LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 379
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 346. Extended Frame Group Start Address register (EFF_GRP_sa - address 0x4003 C010) bit description
Table 347. End of AF Tables register (ENDofTable - address 0x4003 C014) bit description
UM10360
User manual
Bit
1:0
11:2
31:12 -
Bit
1:0
11:2
31:12 -
Symbol
-
Eff_GRP_sa
Symbol
-
EndofTable
16.14.6 Extended Frame Group Start Address register (EFF_GRP_sa -
16.14.7 End of AF Tables register (ENDofTable - 0x4003 C014)
16.14.8 Status registers
[1]
[1]
Description
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The address above the last active address in the last active AF table. For compatibility
with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.
If the eFCAN bit in the AFMR is 0, the largest value that should be written to this
register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM
to be used.
If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance
Filter RAM, into which the Acceptance Filter will automatically receive messages for
selected IDs on selected CAN buses. In this case, the maximum value that should be
written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes
of message storage between this address and the end of Acceptance Filter RAM, for
each Standard ID that is specified between the start of Acceptance Filter RAM, and the
next active AF table.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If
the table is empty, write the same value in this register and the ENDofTable register
described below. The largest value that should be written to this register is 0x800,
when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM
is used. For compatibility with possible future devices, please write zeroes in bits
31:12 and 1:0 of this register.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
[1]
0x4003 C010)
[1]
[1]
The look-up table error status registers, the error addresses, and the flag register provide
information if a programming error in the look-up table RAM during the ID screening was
encountered. The look-up table error address and flag register have only read access. If
an error is detected, the LUTerror flag is set, and the LUTerrorAddr register provides the
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
Write access to the look-up table section configuration registers are possible only during the Acceptance
filter bypass mode or the Acceptance filter off mode.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
0
NA
Reset Value
NA
0
NA
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