LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 225

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 197. USB Device Interrupt Clear register (USBDevIntClr - address 0x5000 C208) bit description
Table 198. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit allocation
Reset value: 0x0000 0000
Table 199. USB Device Interrupt Set register (USBDevIntSet - address 0x5000 C20C) bit description
UM10360
User manual
Bit
31:0
Bit
31:0
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
Symbol
See
USBDevIntClr
bit allocation
table above
Symbol
See
USBDevIntSet
bit allocation
table above
11.10.2.5 USB Device Interrupt Set register (USBDevIntSet - 0x5000 C20C)
11.10.2.6 USB Device Interrupt Priority register (USBDevIntPri - 0x5000 C22C)
TxENDPKT
TxENDPKT
23
15
31
23
15
7
7
-
-
-
-
-
Value
0
1
Value
0
1
Writing one to a bit in this register sets the corresponding bit in the
zero has no effect
USBDevIntSet is a write-only register.
Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no
interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register.
ENDPKT
ENDPKT
Rx
Rx
22
14
30
22
14
Description
No effect.
The corresponding bit in USBDevIntSt
Description
No effect.
The corresponding bit in USBDevIntSt
6
6
-
-
-
-
-
All information provided in this document is subject to legal disclaimers.
CDFULL
CDFULL
21
13
29
21
13
5
5
-
-
-
-
-
Rev. 2 — 19 August 2010
CCEMPTY
CCEMPTY
20
12
28
20
12
4
4
-
-
-
-
-
DEV_STAT
DEV_STAT
(Section
(Section
Chapter 11: LPC17xx USB device controller
19
27
19
11
11
3
3
-
-
-
-
-
11.10.2.2) is cleared.
11.10.2.2) is set.
EP_SLOW
EP_SLOW
18
10
26
18
10
2
2
-
-
-
-
-
EP_FAST
EP_FAST
ERR_INT
ERR_INT
USBDevIntSt
17
25
17
UM10360
9
1
9
1
-
-
-
© NXP B.V. 2010. All rights reserved.
Reset value
0
Reset value
0
EP_RLZED
EP_RLZED
. Writing a
FRAME
FRAME
225 of 840
16
24
16
8
0
8
0
-
-
-