LPC2478 NXP Semiconductors, LPC2478 Datasheet

Page 1

... Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units, and up to 160 fast GPIO lines. The LPC2478 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) allowing the external inputs to generate edge-triggered interrupts ...

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... C-bus interfaces (one with open-drain and two with standard port pins (Inter-IC Sound) interface for digital audio input or output. It can be used with All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... Table 1. Ordering information Type number Package Name LPC2478FBD208 LQFP208 LPC2478FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  LPC2478 Product data sheet Description plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm 0.7 mm All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) LPC2478FBD208 512 LPC2478FET208 512 LPC2478 Product data sheet External Ethernet USB bus OTG/ OHC/ device + 4 kB FIFO 98 Full MII/RMII yes 32-bit 98 Full MII/RMII yes 32-bit All information provided in this document is subject to legal disclaimers. Rev. 3 — ...

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... AD0 A/D CONVERTER D/A CONVERTER AOUT VBAT 2 kB BATTERY RAM power domain 2 RTCX1 RTC RTCX2 OSCILLATOR ALARM WATCHDOG TIMER SYSTEM CONTROL Fig 1. LPC2478 block diagram LPC2478 Product data sheet TMS TDI trace signals TRST TCK TDO EXTIN0 64 kB 512 kB TEST/DEBUG SRAM FLASH INTERFACE ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. LPC2478 pinning LQFP208 package Fig 3. LPC2478 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 P3[27]/D27/ 2 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 9 P1[17]/ENET_MDIO 10 LPC2478 Product data sheet 1 LPC2478FBD208 52 ball A1 index area ...

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... LCDVD[1]/TD2/CAP2[1] LCDVD[2]/TXD3 P3[18]/D18/ 16 P4[12]/A12 PWM0[3]/CTS1 - - TDO 4 P3[12]/D12 V 8 P3[8]/D8 DD(3V3 DD(DCDC)(3V3) SSCORE P2[2]/PWM1[3]/CTS1/ 16 P1[13]/ENET_RX_DV PIPESTAT1/LCDDCLK - - TMS 4 P3[3]/D3 P2[3]/PWM1[4]/DCD1/ 17 P2[6]/PCAP1[0]/RI1/ PIPESTAT2/LCDFP TRACEPKT1/ LCDVD[0]/LCDVD[4] P3[29]/D29/ 4 DBGEN MAT1[0]/PWM1[6] LPC2478 © NXP B.V. 2011. All rights reserved ...

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... SSCORE V 17 P0[17]/CTS1/ DD(3V3) MISO0/MISO V 4 P2[30]/DQMOUT2/ SSIO MAT3[2]/SDA2 P4[7]/A7 17 P0[19]/DSR1/ MCICLK/SDA1 VBAT 4 XTAL1 P0[21]/RI1/ 17 P0[20]/DTR1/ MCIPWR/RD1 MCICMD/SCL1 P2[29]/DQMOUT1 4 XTAL2 V 17 P0[22]/RTS1/ SSIO MCIDAT0/TD1 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 MAT3[1]/MOSI0 P1[18]/USB_UP_LED1 DD(3V3) PWM1[1]/CAP1[0] LPC2478 © NXP B.V. 2011. All rights reserved ...

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... MAT3[0]/MISO0 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 USB_CONNECT2/ SSEL1 P4[2]/A2 12 P1[27]/USB_INT1/ LCDVD[13]/LCDVD[21]/ USB_OVRCR1/CAP0[1] P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ MAT3[0] LCDVD[5]/LCDVD[9]/ LCDVD[19]/MCIDAT3/ I2STX_SDA - - P2[18]/CLKOUT0 4 P0[29]/USB_D+1 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ LCDVD[6]/LCDVD[10]/ LCDVD[8]/LCDVD[12]/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 P0[0]/RD1/TXD3/SDA1 16 P4[3]/ LPC2478 © NXP B.V. 2011. All rights reserved ...

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... O LCDVD[8] — LCD data. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 2 S-bus [17] [17] 2 S-bus [17] © NXP B.V. 2011. All rights reserved. ...

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... HIGH (flashes) when host is enabled and detects activity on the bus. I/O MOSI1 — Master Out Slave In for SSP1. I AD0[7] — A/D converter 0, input 7. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 2 S-bus [17] [17] 2 ...

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... RTS1 — Request to Send output for UART1. I/O MCIDAT0 — Data line 0 for SD/MMC interface. O TD1 — CAN1 transmitter output. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... ENET_TXD2 — Ethernet transmit data 2 (MII interface). O MCICLK — Clock output line for SD/MMC interface. O PWM0[1] — Pulse Width Modulator 0, output 1. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 2 S-bus specification. 2 S-bus specification. 2 ...

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... P1[15] — General purpose digital input/output pin. I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/ Ethernet Receive Clock (MII interface). All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... LCDVD[9]/LCDVD[13] — LCD data. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [18] [18] [18] [18] © NXP B.V. 2011. All rights reserved. ...

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... USB_OVRCR2 — Over-Current status for USB port 2. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [18] [18] [18] [18] 2 C-bus serial clock (OTG transceiver). ...

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... Port 2: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... RD2 — CAN2 receiver input. O RTS1 — Request to Send output for UART1. O TRACEPKT2 — Trace Packet, bit 2. O LCDVD[1]/LCDVD[5] — LCD data. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [19] [19] [19] [19] [19] [19] [19] ...

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... CS3 — LOW active Chip Select 3 signal. I CAP2[1] — Capture input for Timer 2, channel 1. 2 I/O SCL1 — clock input/output (this is not an open-drain pin). All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [19] [19] [19] [19] [20] [20] 2 S-bus specification ...

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... MAT3[2] — Match output for Timer 3, channel 2. 2 I/O SDA2 — data input/output (this is not an open-drain pin). All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... D14 — External memory data line 14. [1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... D25 — External memory data line 25. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... A5 — External memory address line 5. [1] I/O P4[6] — General purpose digital input/output pin. I/O A6 — External memory address line 6. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... A22 — External memory address line 22. O TXD2 — Transmitter output for UART2. I/O MISO1 — Master In Slave Out for SSP1. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2478 being in Reset state. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller , but should be isolated to minimize noise and SSCORE but should be isolated to minimize noise and error. LPC2478 DD(3V3 lines. Open-drain © NXP B.V. 2011. All rights reserved ...

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... This pin has no built-in pull-up and no built-in pull-down resistor. LPC2478 Product data sheet Table 20, Table 21, and Table 20, Table Table 20, Table 21, and All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Table 22. 21, and Table 22. Table 22. Table 20, Table 21, and Table Table 20, ...

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... AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2478 implements two AHBs in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. ...

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... ARM code while retaining most of the ARM’s performance. 7.2 On-chip flash programming memory The LPC2478 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades ...

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... NXP Semiconductors 7.4 Memory map The LPC2478 memory map incorporates several distinct regions as shown in Figure 4. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see Table 5. Address range General use 0x0000 0000 to 0x3FFF FFFF ...

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... FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB SPECIAL REGISTERS RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY 0.0 GB LPC2478 memory map All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 0xFFFF FFFF 0xF000 0000 0xE000 0000 ...

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... External memory controller The LPC2478 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals ...

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... Separate reset domains allow auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.8 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2478 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...

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... The value of the output register may be read back as well as the current state of the port pins. LPC2478 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • ...

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... LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. LPC2478 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2478 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB ...

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... Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC2478 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM all non-control endpoints. ...

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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. LPC2478 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 2 C interface © NXP B.V. 2011. All rights reserved ...

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... Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.15 10-bit DAC The DAC allows the LPC2478 to generate a variable analog output. The maximum output value of the DAC is V 7.15.1 Features • 10-bit DAC • ...

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... UART3 includes an IrDA mode to support infrared communication. 7.17 SPI serial I/O controller The LPC2478 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master ...

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... The I be controlled by more than one bus master connected to it. 2 The I C-bus implemented in LPC2478 supports bit rates up to 400 kbit/s (Fast I 7.20.1 Features • standard I • ...

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... Controls include reset, stop and mute options separately for I 7.22 General purpose 32-bit timers/external event counters The LPC2478 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers ...

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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2478. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...

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... The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2478, the RTC can be clocked by a separate 32.768 kHz oscillator programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3 ...

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... PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed accuracy. Upon power-up or any chip reset, the LPC2478 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.26.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL ...

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... PLL to lock, then connect to the PLL as a clock source. 7.26.3 Wake-up timer The LPC2478 begins operation at power-up and when awakened from Power-down and Deep-power down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...

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... NXP Semiconductors 7.26.4 Power control The LPC2478 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power down-mode and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...

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... If power is supplied to the LPC2478 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2478 will start up when external power is restored ...

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... Code security (Code Read Protection - CRP) This feature of the LPC2478 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. ...

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... If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.27.4 AHB The LPC2478 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM ...

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... The JTAG clock (TCK) must be slower than interface to operate. 7.28.2 Embedded trace Since the LPC2478 have significant amounts of on-chip memories not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Min Max 3.0 3.6 3.0 3.6 0.5 +4.6 0.5 +4.6  ...

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... JEDEC (4.5 in  4 in) 0 m/s 1 m/s 2.5 m/s 8-layer (4.5 in  3 in) 0 m/s 1 m/s 2.5 m/s jc jb All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller (C), can be calculated using the following j and V . The I/O power dissipation Min Typ Max - ...

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... CCLK = 10 MHz CCLK = 72 MHz all peripherals enabled; PCLK = CCLK CCLK = 10 MHz CCLK = 72 MHz [ 3.3 V; DD(DCDC)(3V3 C T amb [3] [4] [3] Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 2.0 3.3 3.6 2.5 3 ...

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... V - DD(3V3) 0.4 [ 4 [ [10 [10 [11 15 50 [11 0.7V - DD(3V3 0.05V DD(3V3) [ [12 LPC2478 Max Unit A 3 A 3 A 3 100 mA 5 DD(3V3 0 0  A 150 85 A  0.3V V DD(3V3 0.4 V A 4  ...

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... GND with 33  series resistor; steady state drive drops below 1  i(VBAT) amb is grounded. DD(3V3 All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [1] Min Typ Max 0.5 1.8 1.95 0.5 1.8 1.95 0.5 1.8 1.95  ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller V = 3.3 V DD(3V3 3.0 V DD(3V3 temperature (° C. versus temperature in Power-down mode DD(IO temperature (° C. amb versus temperature in Power-down BAT LPC2478 002aae049 85 002aae050 85 © NXP B.V. 2011. All rights reserved ...

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... 3 DD(3V3) DD(DCDC)(3V3) amb I/O maximum supply current I DD(IO) mode All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 002aae051 35 60 temperature (°C) at different temperatures DD(DCDC)pd(3V3) 002aae046 35 60 temperature (° C. ...

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... Deep power-down mode All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller temperature (° C amb versus temperature in Deep BAT temperature (°C) DD(DCDC)dpd(3V3) LPC2478 002aae047 85 002aae048 85 versus © NXP B.V. 2011. All rights reserved ...

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... 0.2 Conditions 3.3 V; standard port pins. DD(3V3) All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller 002aaf112 16 I (mA) OH versus HIGH-level output source current OH 002aaf111 °C 25 °C −40 °C 0.4 ...

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... SPI Master mode; see Figure CHCL CLCX CLCH T cy(clk) = 200 mV) i(RMS) All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [1] [2] Min Typ Max 1000  0 cy(clk)  0.4 ...

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... Figure 16 see Figure must reject as EOP; see Figure 16 must accept as EOP; see Figure 16 All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller [2] Min Typ Max 3.96 4.02 4.04 - 32.768 - Min Typ Max 3 ...

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... V to 3.6 V; all voltages are measured with respect to DD(3V3) Conditions [1] [2] powered; < 100 cycles unpowered; < 100 cycles sector or multiple consecutive sectors [2] All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Min Typ Max 10000 100000 - ...

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Static external memory interface Table 15. Dynamic characteristics: Static external memory interface = 40   pF amb DD(DCDC)(3V3) Symbol Parameter Conditions [1] Common to read and write cycles t CS ...

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Table 15. Dynamic characteristics: Static external memory interface = 40   pF amb DD(DCDC)(3V3) Symbol Parameter Conditions t WE HIGH to data invalid WEHDNV time t BLS HIGH to address BLSHANV ...

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... See Figure 18. LPC2478 Product data sheet = 3.6 V, EMC Dynamic Read Config Register = 0x0 DD(DCDC)(3V3) DD(3V3) Conditions All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Min Typ Max [1] - 1.05 1.76 [1] 0.1 1. ...

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... T [1] [1] -  [1] 2 [1] 2 [1] [1] - 3 [1] All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Typ Max  1 cy(CCLK)  cy(CCLK) cy(CCLK)  1 cy(CCLK) 2 cy(CCLK) cy(CCLK)  ...

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... OELOEH t BLSLAV t CSLAV t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller t CSHOEH t h(D) t OEHANV t CSHBLSH 002aad955 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aad956 © NXP B.V. 2011. All rights reserved. ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller extended source EOP width: t receiver EOP width: t sampling edges 002aad326 t h(XXX su(D) h(D) LPC2478 FEOPT , t EOPR1 EOPR2 002aab561 002aad636 © NXP B.V. 2011. All rights reserved ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller Min Typ [1][2][ [1][ [1][ [1][ [1][ [ 19. LPC2478 Max Unit V V DDA 1 pF 1 LSB 2 LSB 3 LSB 0.5 % 4 LSB 40 k Figure 19. © NXP B.V. 2011. All rights reserved ...

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... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller (1) 1018 1019 1020 1021 1022 1023 − i(VREF) SSA 1 LSB = 1024 LPC2478 offset gain error error 1024 002aae604 © NXP B.V. 2011. All rights reserved ...

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... NXP Semiconductors AD0[y] Fig 20. Suggested ADC interface - LPC2478 AD0[y] pin LPC2478 Product data sheet LPC2XXX 20 kΩ SAMPLE SSIO, SSCORE All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller R vsi ...

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... L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC2478 Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Min Typ Max   ...

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... LCDM [1] LCDFP P2[3] [1] LCDDCLK P2[2] [1] LCDLE P2[1] [1] CDPWR P2[0] [2] LCDCLKIN P2[11] All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Color STN single panel LCD function LPC2478 pin used - - - - - - - - - - - - - - - - - - - - ...

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... P2[12] [1] UD[3] P2[9] [1] UD[2] P2[8] [1] UD[1] P2[7] [1] UD[0] P2[6] [1] LCDLP P2[5] [1] LCDENAB/ P2[4] LCDM [1] LCDFP P2[3] [1] LCDDCLK P2[2] [1] LCDLE P2[1] [1] LCDPWR P2[0] [2] LCDCLKIN P2[11] All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller Color STN dual panel LCD function LPC2478 pin used - - - - - - - - - - - - - - - - [4] LD[7] P1[29] [4] LD[6] P1[28] [4] LD[5] P1[27] [4] LD[4] P1[26] [4] LD[3] P1[25] [4] LD[2] P1[24] [4] LD[1] P1[23] [4] LD[0] ...

Page 76

... External interrupt pins EINT1, EINT2, EINT3 replaced by LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced by LCD pins. [4] USB OTG pins replaced by LCD pins pins replaced by LCD pins. LPC2478 Product data sheet TFT 16 bit (1:5:5:5 mode) TFT 24 bit LPC2478 LCD LPC2478 pin pin used function used [4] P1[29] BLUE4 P1[29] [4] P1[28] BLUE3 P1[28] [4] P1[27] ...

Page 77

... NXP Semiconductors 14.2 Suggested USB interface solutions LPC24XX Fig 21. LPC2478 USB interface on a self-powered device LPC24XX Fig 22. LPC2478 USB interface on a bus-powered device LPC2478 Product data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1.5 kΩ V BUS Ω USB_D Ω USB_D− ...

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... RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D−1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D−2 USB_UP_LED2 Fig 23. LPC2478 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2478 Product data sheet RESET_N ADR/PSW OE_N/INT_N V DD ...

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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 24. LPC2478 USB OTG port configuration: VP_VM mode LPC2478 Product data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1302 ADR/PSW SPEED SUSPEND SCL SDA INT_N ...

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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D−1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D−2 V BUS Fig 25. LPC2478 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2478 Product data sheet Ω 33 Ω 15 kΩ 15 kΩ ENA 5 V LM3526 ...

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... USB_D+2 USB_D−2 USB_UP_LED2 Fig 26. LPC2478 USB OTG port configuration: USB port 1 host, USB port 2 host 14.3 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF ...

Page 82

... X2 Maximum crystal series resistance < 300  < 300  < 300  < 300  < 200  < 100  < 160  < 60  < 80  LPC2478 Figure 28 and in and 002aag469 External load capacitors ...

Page 83

... R S 002aaf495 evaluation Figure 29. Since the feedback resistance is and C need to be connected the typical load L and C X1 External load capacitors LPC2478 , Table 25 specified Parasitics L /C components © NXP B.V. 2011. All rights reserved. ...

Page 84

... Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller , and C should be chosen smaller weak pull-up pull-up enable weak pull-down select analog input LPC2478 , and C in case ESD PIN ESD V SS 002aaf496 © NXP B.V. 2011. All rights reserved ...

Page 85

... NXP Semiconductors 14.7 Reset pin configuration Fig 31. Reset pin configuration LPC2478 Product data sheet reset GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller ESD ESD V SS 002aaf274 © ...

Page 86

... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller detail 0.75 1.43 1 0.12 0.08 0.08 0.45 1.08 EUROPEAN PROJECTION LPC2478 SOT459 θ θ 1. 1.08 0 ISSUE DATE 00-02-06 03-02-20 © NXP B.V. 2011. All rights reserved ...

Page 87

... All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 Single-chip 16-bit/32-bit microcontroller detail 0.08 0.12 0.1 EUROPEAN PROJECTION LPC2478 SOT950 ISSUE DATE 06-06-01 06-06-14 © NXP B.V. 2011. All rights reserved ...

Page 88

... Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

Page 89

... Added new table. typ value from 0.5V to 0.05V DD(3V3) interface”: Removed “AHB clock interface”: Swapped min/max interface”: Updated t interface”: Removed “AHB interface”: Added new table. Updated bullets. - LPC2478 v © NXP B.V. 2011. All rights reserved. . DD(3V3) WEHDNV ...

Page 90

... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

Page 91

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... LCD panel signal usage . . . . . . . . . . . . . . . . . 74 14.2 Suggested USB interface solutions . . . . . . . . 77 14.3 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . 81 14.4 RTC 32 kHz oscillator component selection . 83 All information provided in this document is subject to legal disclaimers. Rev. 3 — 12 September 2011 LPC2478 Single-chip 16-bit/32-bit microcontroller © NXP B.V. 2011. All rights reserved ...

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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2478 All rights reserved. Date of release: 12 September 2011 Document identifier: LPC2478 ...