LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 473

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

20.1 Basic configuration
20.2 Features
UM10360
User manual
The I
The I
The I
word select signal. The basic I
and one slave. The I
receive channel, each of which can operate as either a master or a slave.
1. Power: In the PCONP register
2. Clock: In PCLKSEL1 select PCLK_I2S, see
3. Pins: Select I
4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: The I
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UM10360
Chapter 20: LPC17xx I2S
Rev. 2 — 19 August 2010
Remark: On reset, the I
PINMODE4 (see
and
The I
The I
input.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
The sampling frequency (fs) can range (in practice) from 16 to 96 kHz. (16, 22.05, 32,
44.1, 48, or 96 kHz) for audio applications.
Separate Master Clock outputs for both transmit and receive channels support a clock
up to 512 times the I
Word Select period in master mode is configurable (separately for I
output).
Two 8 word (32 byte) FIFO data buffers are provided, one for transmit and one for
receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the General Purpose DMA block.
Controls include reset, stop and mute options separately for I
2
2
2
S interface is configured using the following registers:
S bus provides a standard communication interface for digital audio applications.
S bus specification defines a 3-wire serial bus, having one data, one clock, and one
Table
2
2
S input can operate in both master and slave mode.
S output can operate in both master and slave mode, independent of the I
543.
2
All information provided in this document is subject to legal disclaimers.
S interface supports two DMA requests, see
2
S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
2
S interface on the LPC17xx provides a separate transmit and
Section
Rev. 2 — 19 August 2010
2
S sampling frequency.
2
S interface is disabled (PCI2S = 0).
8.5).
2
S connection has one master, which is always the master,
(Table
46), set bit PCI2S.
Table
41.
Table 410
2
S input and I
© NXP B.V. 2010. All rights reserved.
2
and
S input and I
User manual
Table
2
S output.
473 of 840
411,
2
2
S
S